Merge branch 'x64_new'
This commit is contained in:
commit
d9f311877c
3 changed files with 79 additions and 7 deletions
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@ -290,9 +290,18 @@ extern void cpu_init(void);
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*/
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extern int smp_main(void);
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#ifdef CONFIG_X86_64
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/*
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* 32bit entry point, which jumps to the 64bit code smp_start
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*/
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extern void smp_entry(void);
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#endif
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void smp_start(uint32_t id)
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{
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#ifdef CONFIG_X86_32
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size_t i;
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#endif
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atomic_int32_inc(&cpu_online);
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@ -311,6 +320,8 @@ void smp_start(uint32_t id)
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// install IDT
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idt_install();
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// On 64bit system, paging is already enabled
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#ifdef CONFIG_X86_32
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/* enable paging */
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write_cr3((size_t)get_boot_pgd());
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i = read_cr0();
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@ -320,6 +331,7 @@ void smp_start(uint32_t id)
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// reset APIC and set id
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lapic_reset(); // sets also the timer interrupt
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apic_set_cpu_id(id);
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#endif
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/*
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* we turned on paging
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@ -385,8 +397,13 @@ int smp_init(void)
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{
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// replace 0xDEADC0DE with the address of the smp entry code
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if (*((uint32_t*) (bootaddr+j)) == 0xDEADC0DE) {
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*((uint32_t*) (bootaddr+j)) = (size_t) smp_start;
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kprintf("Set entry point of the application processors at 0x%x\n", (size_t) smp_start);
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#ifdef CONFIG_X86_32
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*((uint32_t*) (bootaddr+j)) = (uint32_t) smp_start;
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kprintf("Set entry point of the application processors at 0x%x\n", (uint32_t) smp_start);
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#else
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*((uint32_t*) (bootaddr+j)) = (uint32_t) smp_entry;
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kprintf("Set entry point of the application processors at 0x%lx\n", (size_t) smp_entry);
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#endif
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}
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// replace APIC ID 0xDEADDEAD
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@ -572,10 +589,8 @@ int apic_calibration(void)
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ioapic_inton(i, apic_processors[boot_processor]->id);
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}
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initialized = 1;
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#ifdef CONFIG_X86_32
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#if MAX_CORES > 1
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smp_init();
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#endif
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#endif
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irq_nested_enable(flags);
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@ -690,7 +705,7 @@ found_mp:
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addr += 20;
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} else if (*((uint8_t*) addr) == 2) { // IO_APIC
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apic_io_entry_t* io_entry = (apic_io_entry_t*) addr;
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ioapic = (ioapic_t*) io_entry->addr;
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ioapic = (ioapic_t*) ((size_t) io_entry->addr);
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addr += 8;
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//kprintf("Found IOAPIC at 0x%x (ver. 0x%x)\n", ioapic, ioapic_read(IOAPIC_REG_VER));
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kprintf("Found IOAPIC at 0x%x\n", ioapic);
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@ -95,6 +95,48 @@ boot_pd times 512 DQ 0
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boot_pt times (NOPTS*512) DQ 0
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SECTION .text
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ALIGN 8
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global smp_entry
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smp_entry:
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; enable caching, disable paging and fpu emulation
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and eax, 0x1ffffffb
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; ...and turn on FPU exceptions
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or eax, 0x22
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mov cr0, eax
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; clears the current pgd entry
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xor eax, eax
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mov cr3, eax
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; at this stage, we disable the SSE support
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mov eax, cr4
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and eax, 0xfffbf9ff
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mov cr4, eax
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; initialize page table
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mov edi, boot_pgd
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mov cr3, edi
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; we need to enable PAE modus
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mov eax, cr4
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or eax, 1 << 5
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mov cr4, eax
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; switch to the compatibility mode (which is part of long mode)
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mov ecx, 0xC0000080
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rdmsr
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or eax, 1 << 8
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wrmsr
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; enable paging
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mov eax, cr0
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or eax, 1 << 31 | 1 << 0 ; Set the PG-bit, which is the 31nd bit, and the PM-bit, which is the 0th bit.
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mov cr0, eax
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mov edi, [esp+4] ; set argumet for smp_start
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lgdt [GDT64.Pointer] ; Load the 64-bit global descriptor table.
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jmp GDT64.Code:smp_start64 ; Set the code segment and enter 64-bit long mode.
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jmp $ ; endless loop
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search_apic:
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push ebp
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mov ebp, esp
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@ -322,11 +364,25 @@ start64:
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extern multiboot_init
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mov rdi, rbx
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call multiboot_init
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; jump to the boot processors's C code
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; jump to the boot processors's C code
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extern main
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call main
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jmp $
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smp_start64:
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; initialize segment registers
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mov ax, GDT64.Data
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mov ds, ax
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mov es, ax
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mov fs, ax
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mov gs, ax
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mov ss, ax
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; jump to the boot processors's C code
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extern smp_start
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call smp_start
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jmp $
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global cpu_init
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cpu_init:
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; mov eax, cr0
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@ -31,7 +31,8 @@ static uint32_t cpu_freq = 0;
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int cpu_detection(void)
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{
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uint32_t a, b, cr4;
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uint32_t a, b;
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size_t cr4;
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cpuid(1, &a, &b, &cpu_info.feature2, &cpu_info.feature1);
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