add SMP support
- this is experimental version - by setting MAX_CORES to 1, you are to disable the SMP support
This commit is contained in:
Stefan Lankes
parent
09b3655ea4
commit
e595fae384
8 changed files with 234 additions and 63 deletions
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@ -187,6 +187,8 @@ typedef struct {
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} dest;
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} __attribute__ ((packed)) ioapic_route_t;
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#define smp_id apic_cpu_id
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int apic_init(void);
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void apic_eoi(void);
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uint32_t apic_cpu_id(void);
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@ -87,6 +87,12 @@ static inline int jump_to_user_code(uint32_t ep, uint32_t stack)
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return 0;
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}
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/** @brief determines the stack of a specific task
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*
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* @return start address of a specific task
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*/
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size_t get_stack(uint32_t id);
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#ifdef __cplusplus
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}
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#endif
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@ -28,7 +28,9 @@
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#include <metalsvm/page.h>
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#include <metalsvm/spinlock.h>
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#include <metalsvm/mmu.h>
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#include <metalsvm/tasks.h>
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#include <asm/irq.h>
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#include <asm/idt.h>
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#include <asm/irqflags.h>
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#include <asm/apic.h>
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#include <asm/multiboot.h>
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@ -36,13 +38,6 @@
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#include <asm/RCCE_lib.h>
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#endif
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/* disable optimization for the following functions */
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//static int apic_send_ipi(uint32_t id, uint32_t mode, uint32_t vector) __attribute__((optimize(0)));
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static int wakeup_all_aps(uint32_t start_eip) __attribute__((optimize(0)));
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//int apic_calibration(void) __attribute__((optimize(0)));
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//int ioapic_intoff(uint8_t irq, uint8_t apicid) __attribute__((optimize(0)));
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//int ioapic_inton(uint8_t irq, uint8_t apicid) __attribute__((optimize(0)));
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// IO APIC MMIO structure: write reg, then read or write data.
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typedef struct {
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uint32_t reg;
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@ -60,12 +55,15 @@ static uint32_t icr = 0;
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static uint32_t ncores = 1;
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static uint8_t irq_redirect[16] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xA, 0xB, 0xC, 0xD, 0xE, 0xF};
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#if MAX_CORES > 1
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static uint8_t boot_code[] = {0xE9, 0x1E, 0x00, 0x17, 0x00, 0x09, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x9A, 0xCF, 0x00, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x92, 0xCF, 0x00, 0x0F, 0x01, 0x16, 0x03, 0x00, 0x0F, 0x20, 0xC0, 0x0C, 0x01, 0x0F, 0x22, 0xC0, 0x66, 0xEA, 0x36, 0x00, 0x01, 0x00, 0x08, 0x00, 0xFA, 0x31, 0xC0, 0x66, 0xB8, 0x10, 0x00, 0x8E, 0xD8, 0x8E, 0xC0, 0x8E, 0xE0, 0x8E, 0xE8, 0x8E, 0xD0, 0x0F, 0x20, 0xC0, 0x25, 0xFF, 0xFF, 0xFF, 0x9F, 0x0D, 0x20, 0x00, 0x00, 0x00, 0x0F, 0x22, 0xC0, 0x31, 0xC0, 0x0F, 0x22, 0xD8, 0xBC, 0xEF, 0xBE, 0xAD, 0xDE, 0x31, 0xC0, 0x31, 0xDB, 0xEA, 0xDE, 0xC0, 0xAD, 0xDE, 0x08, 0x00};
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static uint8_t boot_code[] = { 0xFA, 0x0F, 0x01, 0x16, 0x3B, 0x70, 0x0F, 0x20, 0xC0, 0x0C, 0x01, 0x0F, 0x22, 0xC0, 0x66, 0xEA, 0x16, 0x70, 0x00, 0x00, 0x08, 0x00, 0x31, 0xC0, 0x66, 0xB8, 0x10, 0x00, 0x8E, 0xD8, 0x8E, 0xC0, 0x8E, 0xE0, 0x8E, 0xE8, 0x8E, 0xD0, 0xBC, 0xEF, 0xBE, 0xAD, 0xDE, 0x68, 0xAD, 0xDE, 0xAD, 0xDE, 0x6A, 0x00, 0xEA, 0xDE, 0xC0, 0xAD, 0xDE, 0x08, 0x00, 0xEB, 0xFE, 0x17, 0x00, 0x41, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x9A, 0xCF, 0x00, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x92, 0xCF, 0x00};
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#endif
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static uint8_t initialized = 0;
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static atomic_int32_t cpu_online = ATOMIC_INIT(1);
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spinlock_t bootlock = SPINLOCK_INIT;
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// forward declaration
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static int lapic_reset(void);
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static inline uint32_t lapic_read(uint32_t addr)
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{
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return *((volatile uint32_t*) (lapic+addr));
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@ -110,6 +108,12 @@ uint32_t apic_cpu_id(void)
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return 0;
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}
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static inline void apic_set_cpu_id(uint32_t id)
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{
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if (lapic && initialized)
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lapic_write(APIC_ID, id << 24);
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}
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static inline uint32_t apic_version(void)
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{
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if (lapic)
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@ -137,6 +141,14 @@ int apic_is_enabled(void)
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}
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#if MAX_CORES > 1
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static inline void set_ipi_dest(uint32_t cpu_id) {
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uint32_t tmp;
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tmp = lapic_read(APIC_ICR2);
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tmp &= 0x00FFFFFF;
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tmp |= (cpu_id << 24);
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lapic_write(APIC_ICR2, tmp);
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}
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#if 0
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static int apic_send_ipi(uint32_t id, uint32_t mode, uint32_t vector)
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{
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@ -158,28 +170,49 @@ static int apic_send_ipi(uint32_t id, uint32_t mode, uint32_t vector)
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}
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#endif
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static int wakeup_all_aps(uint32_t start_eip)
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/*
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* use the universal startup algorithm of Intel's MultiProcessor Specification
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*/
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static int wakeup_ap(uint32_t start_eip, uint32_t id)
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{
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static char* reset_vector = 0;
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uint32_t i;
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kputs("Wakeup all application processors via IPI\n");
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kprintf("Wakeup application processor %d via IPI\n", id);
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// set shutdown code to 0x0A
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cmos_write(0x0F, 0x0A);
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if(lapic_read(APIC_ICR1) & APIC_ICR_BUSY) {
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kprintf("ERROR: previous send not complete");
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if (!reset_vector) {
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reset_vector = (char*) map_region(0x00, 0x00, 1, MAP_KERNEL_SPACE|MAP_NO_CACHE);
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reset_vector += 0x467; // add base address of the reset vector
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kprintf("Map reset vector to %p\n", reset_vector);
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}
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*((volatile unsigned short *) (reset_vector+2)) = start_eip >> 4;
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*((volatile unsigned short *) reset_vector) = 0x00;
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if (lapic_read(APIC_ICR1) & APIC_ICR_BUSY) {
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kputs("ERROR: previous send not complete");
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return -EIO;
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}
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vga_puts("Send IPI\n");
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// send out INIT to all aps
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lapic_write(APIC_ICR1, APIC_INT_ASSERT|APIC_DEST_ALLBUT|APIC_DM_INIT);
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//kputs("Send IPI\n");
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// send out INIT to AP
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set_ipi_dest(id);
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lapic_write(APIC_ICR1, APIC_INT_LEVELTRIG|APIC_INT_ASSERT|APIC_DM_INIT);
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udelay(200);
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// reset INIT
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lapic_write(APIC_ICR1, APIC_INT_LEVELTRIG|APIC_DM_INIT);
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udelay(10000);
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// send out the startup
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lapic_write(APIC_ICR1, APIC_INT_ASSERT|APIC_DEST_ALLBUT|APIC_DM_STARTUP|(start_eip >> 12));
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set_ipi_dest(id);
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lapic_write(APIC_ICR1, APIC_DM_STARTUP|(start_eip >> 12));
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udelay(200);
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// do it again
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lapic_write(APIC_ICR1, APIC_INT_ASSERT|APIC_DEST_ALLBUT|APIC_DM_STARTUP|(start_eip >> 12));
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set_ipi_dest(id);
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lapic_write(APIC_ICR1, APIC_DM_STARTUP|(start_eip >> 12));
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udelay(200);
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vga_puts("IPI done...\n");
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//kputs("IPI done...\n");
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i = 0;
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while((lapic_read(APIC_ICR1) & APIC_ICR_BUSY) && (i < 1000))
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@ -190,12 +223,65 @@ static int wakeup_all_aps(uint32_t start_eip)
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#endif
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#if MAX_CORES > 1
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static void smp_main(void)
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/*
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* This is defined in entry.asm. We use this to properly reload
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* the new segment registers
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*/
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extern void gdt_flush(void);
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/*
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* This is defined in entry.asm and initialized the processors.
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*/
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extern void cpu_init(void);
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/*
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* platform independent entry point of the application processors
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*/
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extern int smp_main(void);
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void smp_start(uint32_t id)
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{
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vga_puts("JJAJAJAJAJAJA\n");
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lowlevel_init();
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uint32_t i;
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atomic_int32_inc(&cpu_online);
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kputs("JAJAJAJ\n");
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// reset APIC and set id
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lapic_reset();
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apic_set_cpu_id(id);
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kprintf("Application processor %d is entering its idle task\n", apic_cpu_id());
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// initialize default cpu features
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cpu_init();
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// use the same gdt like the boot processors
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gdt_flush();
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// install IDT
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idt_install();
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// enable additional cpu features
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cpu_detection();
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/* enable paging */
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write_cr3((uint32_t)get_boot_pgd());
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i = read_cr0();
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i = i | (1 << 31);
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write_cr0(i);
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// reset APIC and set id
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lapic_reset(); // sets also the timer interrupt
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apic_set_cpu_id(id);
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/*
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* we turned on paging
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* => now, we are able to register our task for Task State Switching
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*/
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register_task(per_core(current_task));
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smp_main();
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// idle loop
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while(1) ;
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}
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#endif
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@ -218,37 +304,59 @@ static unsigned int* search_apic(unsigned int base, unsigned int limit) {
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#if MAX_CORES > 1
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int smp_init(void)
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{
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uint32_t i;
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size_t bootaddr;
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uint32_t i, j;
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char* bootaddr;
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int err;
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if (ncores <= 1)
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return -EINVAL;
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/*
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* dirty hack: Copy 16bit startup code (see tools/smp_setup.asm)
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* to a 16bit address. Wakeup the other cores via IPI. They start
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* at this address in real mode, switch to protected and finally
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* they jump to smp_main.
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*/
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bootaddr = 0x10000;
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map_region(bootaddr, get_pages(1), 1, MAP_KERNEL_SPACE);
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for(i=0; i<sizeof(boot_code); i+=sizeof(size_t))
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for(i=1; (i<ncores) && (i<MAX_CORES); i++)
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{
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// replace 0xDEADC0DE with the address of the smp entry code
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if (*((size_t*) (bootaddr+i)) == 0xDEADC0DE)
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*((size_t*) (bootaddr+i)) = (size_t) smp_main;
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/*
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* dirty hack: Copy 16bit startup code (see tools/smp_setup.asm)
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* to a 16bit address. Wakeup the other cores via IPI. They start
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* at this address in real mode, switch to protected and finally
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* they jump to smp_main.
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*
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* The page at SMP_SETUP_ADDR is already reserved for this hack!
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*/
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bootaddr = (char*) SMP_SETUP_ADDR;
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memcpy(bootaddr, boot_code, sizeof(boot_code));
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for(j=0; j<sizeof(boot_code)-4; j++)
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{
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// replace 0xDEADC0DE with the address of the smp entry code
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if (*((size_t*) (bootaddr+j)) == 0xDEADC0DE) {
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*((size_t*) (bootaddr+j)) = (size_t) smp_start;
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kprintf("Set entry point of the application processors at 0x%x\n", (size_t) smp_start);
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}
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// replace APIC ID 0xDEADDEAD
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if (*((size_t*) (bootaddr+j)) == 0xDEADDEAD)
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*((size_t*) (bootaddr+j)) = i;
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// replace 0xDEADBEEF with the addres of the stack
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if (*((size_t*) (bootaddr+j)) == 0xDEADBEEF) {
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uint32_t esp = get_idle_task(i);
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*((size_t*) (bootaddr+j)) = esp;
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if ((int) esp < 0)
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kprintf("Invalid stack value\n");
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kprintf("Set stack of the application processors to 0x%x\n", esp);
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}
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}
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//kprintf("size of the boot_code %d\n", sizeof(boot_code));
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err = wakeup_ap((uint32_t)bootaddr, i);
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if (err)
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kprintf("Unable to wakeup application processor %d: %d\n", i, err);
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j = 0;
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while((ncores != atomic_int32_read(&cpu_online)) && (j < 100)) {
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udelay(1000);
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j++;
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}
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}
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kprintf("size of the boot_code %d\n", sizeof(boot_code));
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err = wakeup_all_aps(bootaddr);
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if (err)
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kprintf("Unable to wakeup application processors: %d\n", err);
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i = 0;
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while((ncores != atomic_int32_read(&cpu_online)) && (i < 1000))
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i++;
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kprintf("%d cores online\n", atomic_int32_read(&cpu_online));
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return 0;
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@ -379,9 +487,6 @@ int apic_calibration(void)
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kprintf("APIC calibration determines an ICR of 0x%x\n", icr);
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flags = irq_nested_disable();
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#if MAX_CORES > 1
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//smp_init();
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#endif
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if (ioapic) {
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// now, we don't longer need the IOAPIC timer and turn it off
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@ -391,6 +496,9 @@ int apic_calibration(void)
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ioapic_inton(i, apic_processors[boot_processor]->id);
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}
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initialized = 1;
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#if MAX_CORES > 1
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smp_init();
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#endif
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irq_nested_enable(flags);
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return 0;
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@ -34,11 +34,18 @@ static gdt_entry_t gdt[GDT_ENTRIES] = {[0 ... GDT_ENTRIES-1] = {0, 0, 0, 0, 0,
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unsigned char* default_stack_pointer __attribute__ ((section (".data"))) = kstacks[0] + KERNEL_STACK_SIZE - sizeof(size_t);
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/*
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* This is in start.asm. We use this to properly reload
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* This is defined in entry.asm. We use this to properly reload
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* the new segment registers
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*/
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extern void gdt_flush(void);
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size_t get_stack(uint32_t id)
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{
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if (BUILTIN_EXPECT(id >= MAX_TASKS, 0))
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return -EINVAL;
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return (size_t) kstacks[id] + KERNEL_STACK_SIZE - sizeof(size_t);
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}
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int register_task(task_t* task) {
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uint16_t sel;
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uint32_t id = task->id;
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@ -74,13 +74,19 @@ extern void isrsyscall(void);
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/* Installs the IDT */
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void idt_install(void)
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{
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/* Sets the special IDT pointer up, just like in 'gdt.c' */
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idtp.limit = (sizeof(idt_entry_t) * 256) - 1;
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idtp.base = (unsigned int)&idt;
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static int initialized = 0;
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/* Add any new ISRs to the IDT here using idt_set_gate */
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idt_set_gate(INT_SYSCALL, (unsigned int)isrsyscall, KERNEL_CODE_SELECTOR,
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IDT_FLAG_PRESENT|IDT_FLAG_RING3|IDT_FLAG_32BIT|IDT_FLAG_TRAPGATE);
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if (!initialized) {
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initialized = 1;
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/* Sets the special IDT pointer up, just like in 'gdt.c' */
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idtp.limit = (sizeof(idt_entry_t) * 256) - 1;
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idtp.base = (unsigned int)&idt;
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/* Add any new ISRs to the IDT here using idt_set_gate */
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idt_set_gate(INT_SYSCALL, (unsigned int)isrsyscall, KERNEL_CODE_SELECTOR,
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IDT_FLAG_PRESENT|IDT_FLAG_RING3|IDT_FLAG_32BIT|IDT_FLAG_TRAPGATE);
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}
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/* Points the processor's internal register to the new IDT */
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asm volatile("lidt %0" : : "m" (idtp));
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@ -126,6 +126,16 @@ void NORETURN sys_exit(int);
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* */
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int sys_fork(void);
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/** @brief Reserve an idel task for an additional core
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*
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* @param id core number
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*
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* return
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* - address of the stack (< KERNEL_SPACE)
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* - -ENIVAL (-22) on failure
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*/
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size_t get_idle_task(uint32_t id);
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/** @brief System call to execute a program
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*
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* @param fname Filename of the executable
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@ -78,6 +78,20 @@ static void list_root(void) {
|
|||
list_fs(fs_root, 1);
|
||||
}
|
||||
|
||||
#if MAX_CORES > 1
|
||||
// idle loop of the application processors
|
||||
int smp_main(void)
|
||||
{
|
||||
irq_enable();
|
||||
|
||||
while(1) {
|
||||
HALT;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int main(void)
|
||||
{
|
||||
lowlevel_init();
|
||||
|
|
|
|||
|
|
@ -66,15 +66,36 @@ int multitasking_init(void) {
|
|||
atomic_int32_set(&task_table[0].user_usage, 0);
|
||||
mailbox_wait_msg_init(&task_table[0].inbox);
|
||||
memset(task_table[0].outbox, 0x00, sizeof(mailbox_wait_msg_t*)*MAX_TASKS);
|
||||
per_core(current_task) = task_table+0;
|
||||
per_core(current_task)->pgd = get_boot_pgd();
|
||||
task_table[0].pgd = get_boot_pgd();
|
||||
task_table[0].flags = TASK_DEFAULT_FLAGS;
|
||||
per_core(current_task) = task_table+0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
size_t get_idle_task(uint32_t id)
|
||||
{
|
||||
#if MAX_CORES > 1
|
||||
if (BUILTIN_EXPECT((id >= MAX_TASKS) || (task_table[id].status != TASK_INVALID), 0))
|
||||
return -EINVAL;
|
||||
|
||||
task_table[id].id = id;
|
||||
task_table[id].status = TASK_IDLE;
|
||||
atomic_int32_set(&task_table[id].user_usage, 0);
|
||||
mailbox_wait_msg_init(&task_table[id].inbox);
|
||||
memset(task_table[id].outbox, 0x00, sizeof(mailbox_wait_msg_t*)*MAX_TASKS);
|
||||
task_table[id].pgd = get_boot_pgd();
|
||||
task_table[id].flags = TASK_DEFAULT_FLAGS;
|
||||
current_task[id].var = task_table+id;
|
||||
|
||||
return get_stack(id);
|
||||
#else
|
||||
return -EINVAL;
|
||||
#endif
|
||||
}
|
||||
|
||||
/** @brief Wakeup tasks which are waiting for a message from the current one
|
||||
*
|
||||
* @param result Current task's resulting return value
|
||||
|
|
@ -744,14 +765,11 @@ void scheduler(void)
|
|||
* we switch to the idle task, if the current task terminates
|
||||
* and no other is ready
|
||||
*/
|
||||
for(i=0; i<MAX_TASKS; i++) {
|
||||
if (task_table[i].status == TASK_IDLE) {
|
||||
per_core(current_task) = task_table+i;
|
||||
goto get_task_out;
|
||||
}
|
||||
}
|
||||
per_core(current_task) = task_table+smp_id();
|
||||
|
||||
get_task_out:
|
||||
//kprintf("schedule %d on core %d\n", per_core(current_task)->id, smp_id());
|
||||
|
||||
#if MAX_CORES > 1
|
||||
spinlock_irqsave_unlock(&table_lock);
|
||||
#else
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue