From e599063dd2f54cc8923b327751f3bd6e8ca5ce65 Mon Sep 17 00:00:00 2001 From: Stefan Lankes Date: Tue, 5 Apr 2011 11:37:20 +0200 Subject: [PATCH] cosmetic changes --- arch/x86/kernel/apic.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/x86/kernel/apic.c b/arch/x86/kernel/apic.c index b2edcebd..f7eee024 100644 --- a/arch/x86/kernel/apic.c +++ b/arch/x86/kernel/apic.c @@ -286,13 +286,13 @@ int apic_calibration(void) lapic_write(APIC_DCR, 0xB); // set it to 1 clock increments lapic_write(APIC_LVT_T, 0x2007B); // connects the timer to 123 and enables it - lapic_write(APIC_ICR, 0xFFFFFFFF); + lapic_write(APIC_ICR, 0xFFFFFFFFUL); /* wait 3 time slices to determine a ICR */ while(get_clock_tick() - ticks < 3) ; - diff = 0xFFFFFFFF - lapic_read(APIC_CCR); + diff = 0xFFFFFFFFUL - lapic_read(APIC_CCR); diff = diff / 3; lapic_write(APIC_DCR, 0xB); // set it to 1 clock increments @@ -323,7 +323,7 @@ int apic_calibration(void) lapic_write(APIC_DCR, 0xB); // set it to 1 clock increments lapic_write(APIC_LVT_T, 0x2007B); // connects the timer to 123 and enables it - lapic_write(APIC_ICR, 0xFFFFFFFF); + lapic_write(APIC_ICR, 0xFFFFFFFFUL); /* wait 3 time slices to determine a ICR */ start = rdtsc(); @@ -331,9 +331,9 @@ int apic_calibration(void) flush_pipeline(); end = rdtsc(); ticks = end > start ? end - start : start - end; - } while(ticks*TIMER_FREQ < 3*RC_REFCLOCKMHZ*1000000); + } while(ticks*TIMER_FREQ < 3*RC_REFCLOCKMHZ*1000000UL); - diff = 0xFFFFFFFF - lapic_read(APIC_CCR); + diff = 0xFFFFFFFFUL - lapic_read(APIC_CCR); diff = diff / 3; lapic_write(APIC_DCR, 0xB); // set it to 1 clock increments