diff --git a/arch/x86/scc/scc_init.c b/arch/x86/scc/scc_init.c
index 28115009..dc61437c 100644
--- a/arch/x86/scc/scc_init.c
+++ b/arch/x86/scc/scc_init.c
@@ -23,6 +23,7 @@
 #include <metalsvm/errno.h>
 #include <asm/io.h>
 #include <asm/RCCE_lib.h>
+#include <asm/SCC_API.h>
 
 #ifdef CONFIG_ROCKCREEK
 
@@ -32,6 +33,40 @@
 static char*	rcce_argv[] = {"MetalSVM", "1", "533", "0"};
 static int 	rcce_argc = 4;
 
+/*
+ * This is a modified MPB program, which is part of the RCCE distribution (src/mpb.c).
+ */
+static int scc_reset(void)
+{
+	int tmp, x, y, z, offset;
+
+	// Initialize API
+	InitAPI(0);
+  
+	// Find out who I am...
+	tmp=ReadConfigReg(CRB_OWN+MYTILEID); 
+	x=(tmp>>3) & 0x0f; // bits 06:03
+	y=(tmp>>7) & 0x0f; // bits 10:07
+	z=(tmp   ) & 0x07; // bits 02:00
+
+	// Allocate Message Passing Buffer
+	t_vcharp MPB;
+	MPBalloc(&MPB, x, y, z, 1); 
+	if (!MPB) {
+		kprintf("Unable to allocate MPB for core %d of Tile x=%d, y= %d! Exiting.\n", z, x, y);
+		return 255;
+	}
+
+	// zap own MPB
+	for (offset=0; offset < 0x2000; offset+=8)
+		*(volatile unsigned long long int*)(MPB+offset) = 0;
+
+	// Clear test&set register write. Next read-access will read "1" (lock granted).
+	SetConfigReg(CRB_ADDR(x,y)+((z)?LOCK1:LOCK0), 1); 
+
+	return 0;
+}
+
 int scc_init(void)
 {
 //	uint32_t x, y, z;