- redesign of the apic code
- add ioapic support - currently, all irq will forwarded to the boot processor git-svn-id: http://svn.lfbs.rwth-aachen.de/svn/scc/trunk/MetalSVM@293 315a16e6-25f9-4109-90ae-ca3045a26c18
This commit is contained in:
stefan
parent
3e1c151b5f
commit
f28fd84c68
6 changed files with 386 additions and 55 deletions
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@ -40,7 +40,7 @@ typedef struct {
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typedef struct {
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uint32_t signature;
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uint16_t length;
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uint8_t revision;
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uint8_t revision;
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uint8_t checksum;
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uint8_t oem_id[8];
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uint8_t product_id[12];
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@ -49,15 +49,15 @@ typedef struct {
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uint16_t entry_count;
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uint32_t lapic;
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uint16_t extended_table_length;
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uint8_t extended_table_checksum;
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uint8_t extended_table_checksum;
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} __attribute__ ((packed)) apic_config_table_t;
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/* APIC Processor Entry */
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typedef struct {
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uint8_t type;
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uint8_t type;
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uint8_t id;
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uint8_t version;
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uint8_t cpu;
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uint8_t cpu_flags;
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uint32_t cpu_signature;
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uint32_t cpu_feature;
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} __attribute__ ((packed)) apic_processor_entry_t;
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@ -71,13 +71,67 @@ typedef struct {
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uint32_t addr;
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} __attribute__ ((packed)) apic_io_entry_t;
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/* Bus Entry */
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typedef struct {
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uint8_t type;
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uint8_t bus_id;
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char name[6];
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} __attribute__ ((packed)) apic_bus_entry_t;
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/* I/O Interrupt Assignment Entry */
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typedef struct {
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uint8_t type; // type = 3
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uint8_t itype; // interrupt type
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uint16_t flags; // flags , PO and EL
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uint8_t src_bus; // source bus id
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uint8_t src_irq; // source interrupt (from the old bus)
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uint8_t dest_apic; // who it gets sent to 0xFF == all
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uint8_t dest_intin; // which pin it gets sent to on the IO APIC
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} __attribute__ ((packed)) apic_ioirq_entry_t;
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typedef struct {
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union {
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struct {
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uint32_t vector : 8,
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delivery_mode : 3, /* 000: FIXED
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* 001: lowest prio
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* 111: ExtINT
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*/
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dest_mode : 1, /* 0: physical, 1: logical */
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delivery_status : 1,
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polarity : 1,
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irr : 1,
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trigger : 1, /* 0: edge, 1: level */
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mask : 1, /* 0: enabled, 1: disabled */
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__reserved_2 : 15;
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} bitfield;
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uint32_t whole;
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} lower;
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union {
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struct {
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uint32_t __reserved_1 : 24,
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physical_dest : 4,
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__reserved_2 : 4;
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} physical;
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struct {
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uint32_t __reserved_1 : 24,
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logical_dest : 8;
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} logical;
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uint32_t upper;
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} dest;
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} __attribute__ ((packed)) ioapic_route_t;
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int apic_init(void);
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void apic_eoi(void);
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uint32_t apic_cpu_id(void);
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int apic_calibration(void);
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int has_apic(void);
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int apic_is_enabled(void);
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int ioapic_inton(uint8_t irq, uint8_t apicid);
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int ioapic_intoff(uint8_t irq, uint8_t apicid);
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#ifdef __cplusplus
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}
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#endif
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#endif
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@ -30,6 +30,7 @@
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#define MP_FLT_SIGNATURE 0x5f504d5f
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#define APIC_ID 0x0020 // Local APIC ID Register
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#define APIC_VERSION 0x0030 // Local APIC Version Register
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#define APIC_TPR 0x0080 // Task Priority Regster
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#define APIC_EOI 0x00B0 // EOI Register
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@ -43,14 +44,58 @@
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#define APIC_CCR 0x0390 // Current Count Register
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#define APIC_DCR 0x03E0 // Divide Configuration Register
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#define IOAPIC_REG_ID 0x0000 // Register index: ID
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#define IOAPIC_REG_VER 0x0001 // Register index: version
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#define IOAPIC_REG_TABLE 0x0010 // Redirection table base
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// IO APIC MMIO structure: write reg, then read or write data.
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typedef struct {
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uint32_t reg;
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uint32_t pad[3];
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uint32_t data;
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} ioapic_t;
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static const apic_processor_entry_t* apic_processors[MAX_CORES] = {[0 ... MAX_CORES-1] = NULL};
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static uint32_t boot_processor = MAX_CORES;
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static apic_mp_t* apic_mp = NULL;
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static apic_config_table_t* apic_config = NULL;
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static uint32_t lapic = 0;
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static volatile ioapic_t* ioapic = NULL;
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static uint32_t ncores = 1;
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static uint8_t irq_redirect[16] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xA, 0xB, 0xC, 0xD, 0xE, 0xF};
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static uint8_t initialized = 0;
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static inline void apic_write(uint32_t addr, uint32_t value)
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static inline uint32_t lapic_read(uint32_t addr)
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{
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asm volatile ("movl (%%eax), %%edx; movl %%ebx, (%%eax)" :: "a"(addr), "b"(value) : "%edx");
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return *((uint32_t*) (lapic+addr));
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}
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static inline void lapic_write(uint32_t addr, uint32_t value)
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{
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/*
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* to avoid ap entium bug, we have to read a apic register before
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* before we write value to this register
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*/
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asm volatile ("movl (%%eax), %%edx; movl %%ebx, (%%eax)" :: "a"(addr+lapic), "b"(value) : "%edx");
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//*((uint32_t*) (lapic+addr)) = value;
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}
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static inline uint32_t ioapic_read(uint32_t reg)
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{
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ioapic->reg = reg;
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return ioapic->data;
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}
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static inline void ioapic_write(uint32_t reg, uint32_t value)
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{
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ioapic->reg = reg;
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ioapic->data = value;
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}
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uint32_t apic_cpu_id(void)
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{
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return ((lapic_read(APIC_ID)) >> 24);
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}
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#ifndef CONFIG_MULTIBOOT
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@ -73,8 +118,8 @@ static unsigned int* search_apic(unsigned int base, unsigned int limit) {
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*/
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void apic_eoi(void)
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{
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if (lapic)
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apic_write(lapic+APIC_EOI, 0);
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if (BUILTIN_EXPECT(lapic, 1))
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lapic_write(APIC_EOI, 0);
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}
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/*
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@ -83,6 +128,8 @@ void apic_eoi(void)
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*/
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int apic_calibration(void)
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{
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uint8_t i;
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#ifndef CONFIG_ROCKCREEK
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uint64_t ticks, old;
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uint32_t diff;
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@ -96,9 +143,9 @@ int apic_calibration(void)
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while((ticks = get_clock_tick()) - old == 0)
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;
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apic_write(lapic+APIC_DCR, 0xB); // set it to 1 clock increments
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apic_write(lapic+APIC_LVT_T, 0x20030); // connects the timer to 48 and enables it
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apic_write(lapic+APIC_ICR, 0xFFFFFFFF);
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lapic_write(APIC_DCR, 0xB); // set it to 1 clock increments
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lapic_write(APIC_LVT_T, 0x2007B); // connects the timer to 123 and enables it
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lapic_write(APIC_ICR, 0xFFFFFFFF);
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/* wait 3 time slices to determine a ICR */
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while(get_clock_tick() - ticks < 3)
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@ -106,9 +153,9 @@ int apic_calibration(void)
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diff = 0xFFFFFFFF - *((uint32_t*) (lapic+APIC_CCR));
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apic_write(lapic+APIC_DCR, 0xB); // set it to 1 clock increments
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apic_write(lapic+APIC_LVT_T, 0x20030); // connects the timer to 48 and enables it
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apic_write(lapic+APIC_ICR, diff / 3);
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lapic_write(APIC_DCR, 0xB); // set it to 1 clock increments
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lapic_write(APIC_LVT_T, 0x2007B); // connects the timer to 123 and enables it
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lapic_write(APIC_ICR, diff / 3);
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// Now, MetalSVM is able to use the APIC => Therefore, we disable the PIC
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outportb(0xA1, 0xFF);
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@ -125,9 +172,9 @@ int apic_calibration(void)
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if (!has_apic())
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return -ENXIO;
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apic_write(lapic+APIC_DCR, 0xB); // set it to 1 clock increments
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apic_write(lapic+APIC_LVT_T, 0x20030); // connects the timer to 48 and enables it
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apic_write(lapic+APIC_ICR, 0xFFFFFFFF);
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lapic_write(APIC_DCR, 0xB); // set it to 1 clock increments
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lapic_write(APIC_LVT_T, 0x2007B); // connects the timer to 123 and enables it
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lapic_write(APIC_ICR, 0xFFFFFFFF);
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/* wait 3 time slices to determine a ICR */
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start = rdtsc();
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@ -139,13 +186,24 @@ int apic_calibration(void)
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diff = 0xFFFFFFFF - *((uint32_t*) (lapic+APIC_CCR));
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apic_write(lapic+APIC_DCR, 0xB); // set it to 1 clock increments
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apic_write(lapic+APIC_LVT_T, 0x20030); // connects the timer to 48 and enables it
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apic_write(lapic+APIC_ICR, diff / 3);
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lapic_write(APIC_DCR, 0xB); // set it to 1 clock increments
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lapic_write(APIC_LVT_T, 0x2007B); // connects the timer to 123 and enables it
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lapic_write(APIC_ICR, diff / 3);
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#endif
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kprintf("APIC calibration detects an ICR of 0x%x\n", diff / 3);
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irq_disable();
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if (ioapic) {
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// now, we don't longer need the IOAPIC timer and turn it off
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ioapic_intoff(0, apic_processors[boot_processor]->id);
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// now lets turn everything else on
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for(i=1; i<24; i++)
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ioapic_inton(i, apic_processors[boot_processor]->id);
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}
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initialized = 1;
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irq_enable();
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return 0;
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}
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@ -153,6 +211,7 @@ static int apic_probe(void)
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{
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size_t addr;
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uint32_t i, count;
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int isa_bus = -1;
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// searching MP signature in the reserved memory areas
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#ifdef CONFIG_MULTIBOOT
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@ -200,15 +259,59 @@ found_mp:
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goto no_mp;
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}
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addr = (size_t) apic_config;
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addr += sizeof(apic_config_table_t);
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if (addr % 4)
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addr += 4 - addr % 4;
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// search the ISA bus => required to redirect the IRQs
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for(i=0; i<apic_config->entry_count; i++) {
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switch(*((uint8_t*) addr)) {
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case 0:
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addr += 20;
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break;
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case 1: {
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apic_bus_entry_t* mp_bus;
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mp_bus = (apic_bus_entry_t*) addr;
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if (mp_bus->name[0] == 'I' && mp_bus->name[1] == 'S' &&
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mp_bus->name[2] == 'A')
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isa_bus = i;
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}
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default:
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addr += 8;
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}
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}
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addr = (size_t) apic_config;
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addr += sizeof(apic_config_table_t);
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if (addr % 4)
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addr += 4 - addr % 4;
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for(i=0, count=0; i<apic_config->entry_count; i++) {
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if (*((uint8_t*) addr) == 0) {
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if (*((uint8_t*) addr) == 0) { // cpu entry
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if (i < MAX_CORES) {
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apic_processors[i] = (apic_processor_entry_t*) addr;
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if (!(apic_processors[i]->cpu_flags & 0x01)) // is the processor usable?
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apic_processors[i] = NULL;
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else if (apic_processors[i]->cpu_flags & 0x02)
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boot_processor = i;
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}
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count++;
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addr += 20;
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} else if (*((uint8_t*) addr) == 2) { // IO_APIC
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apic_io_entry_t* io_entry = (apic_io_entry_t*) addr;
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ioapic = (ioapic_t*) io_entry->addr;
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addr += 8;
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kprintf("Found IOAPIC at 0x%x (ver. 0x%x)\n", ioapic,
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ioapic_read(IOAPIC_REG_VER));
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} else if (*((uint8_t*) addr) == 3) { // IO_INT
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apic_ioirq_entry_t* extint = (apic_ioirq_entry_t*) addr;
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if (extint->src_bus == isa_bus) {
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irq_redirect[extint->src_irq] = extint->dest_intin;
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kprintf("Redirect irq %u -> %u\n", extint->src_irq, extint->dest_intin);
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}
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addr += 8;
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} else addr += 8;
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}
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kprintf("Found %u cores\n", count);
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@ -223,13 +326,11 @@ check_lapic:
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if (apic_config) {
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lapic = apic_config->lapic;
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} else {
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uint32_t eax, edx, dummy;
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uint32_t edx, dummy;
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cpuid(0x1, &eax, &dummy, &dummy, &edx);
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cpuid(0x1, &dummy, &dummy, &dummy, &edx);
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if (edx & (1 << 9))
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lapic = 0xFEE00000;
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kprintf("Processor familiy %u, model %u, stepping %u\n", (eax>>8)&0xF, (eax>>4)&0xF, eax&0xF);
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}
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if (!lapic)
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@ -259,18 +360,27 @@ no_mp:
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int apic_init(void)
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{
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int ret;
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uint8_t i;
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ret = apic_probe();
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if (!ret)
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return ret;
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apic_write(lapic+APIC_TPR, 0x00); // allow all interrupts
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apic_write(lapic+APIC_LVT_T, 0x10000); // disable timer interrupt
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apic_write(lapic+APIC_LVT_PMC, 0x10000);// disable performance counter interrupt
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apic_write(lapic+APIC_LINT0, 0x31); // connect LINT0 to idt entry 49
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apic_write(lapic+APIC_LINT1, 0x32); // connect LINT1 to idt entry 50
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apic_write(lapic+APIC_LVT_ER, 0x33); // connect error to idt entry 51
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apic_write(lapic+APIC_SVR, 0x17F); // enable the apic and connect to the idt entry 207
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lapic_write(APIC_TPR, 0x00); // allow all interrupts
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lapic_write(APIC_LVT_T, 0x10000); // disable timer interrupt
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lapic_write(APIC_LVT_PMC, 0x10000);// disable performance counter interrupt
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lapic_write(APIC_LINT0, 0x7C); // connect LINT0 to idt entry 124
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lapic_write(APIC_LINT1, 0x7D); // connect LINT1 to idt entry 125
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lapic_write(APIC_LVT_ER, 0x7E); // connect error to idt entry 126
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lapic_write(APIC_SVR, 0x17F); // enable the apic and connect to the idt entry 127
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if (ioapic) {
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// enable timer interrupt
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ioapic_inton(0, apic_processors[boot_processor]->id);
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// now lets turn everything else off
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for(i=1; i<24; i++)
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ioapic_intoff(i, apic_processors[boot_processor]->id);
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}
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return 0;
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}
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@ -279,3 +389,71 @@ int has_apic(void)
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{
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return (lapic != 0);
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}
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int apic_is_enabled(void)
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{
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return ((lapic != 0) && initialized);
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}
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int ioapic_inton(uint8_t irq, uint8_t apicid)
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{
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ioapic_route_t route;
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uint32_t off;
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if (BUILTIN_EXPECT(irq > 24, 0)){
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kprintf("IOAPIC: trying to turn on irq %i which is too high\n", irq);
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return -EINVAL;
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}
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if (irq < 16)
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off = irq_redirect[irq]*2;
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else
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off = irq*2;
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route.lower.bitfield.dest_mode = 0;
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route.lower.bitfield.mask = 0;
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route.dest.physical.physical_dest = apicid; // send to the boot processor
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route.lower.bitfield.delivery_mode = 0;
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route.lower.bitfield.polarity = 0;
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route.lower.bitfield.trigger = 0;
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route.lower.bitfield.vector = 0x20+irq;
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route.lower.bitfield.mask = 0; // turn it on (stop masking)
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ioapic_write(IOAPIC_REG_TABLE+off, route.lower.whole);
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ioapic_write(IOAPIC_REG_TABLE+1+off, route.dest.upper);
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route.dest.upper = ioapic_read(IOAPIC_REG_TABLE+1+off);
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route.lower.whole = ioapic_read(IOAPIC_REG_TABLE+off);
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return 0;
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}
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int ioapic_intoff(uint8_t irq, uint8_t apicid)
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{
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ioapic_route_t route;
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uint32_t off;
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|
||||
if (BUILTIN_EXPECT(irq > 24, 0)){
|
||||
kprintf("IOAPIC: trying to turn on irq %i which is too high\n", irq);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (irq < 16)
|
||||
off = irq_redirect[irq]*2;
|
||||
else
|
||||
off = irq*2;
|
||||
|
||||
route.lower.bitfield.dest_mode = 0;
|
||||
route.lower.bitfield.mask = 0;
|
||||
route.dest.physical.physical_dest = apicid;
|
||||
route.lower.bitfield.delivery_mode = 0;
|
||||
route.lower.bitfield.polarity = 0;
|
||||
route.lower.bitfield.trigger = 0;
|
||||
route.lower.bitfield.vector = 0x20+irq;
|
||||
route.lower.bitfield.mask = 1; // turn it off (start masking)
|
||||
|
||||
ioapic_write(IOAPIC_REG_TABLE+off, route.lower.whole);
|
||||
ioapic_write(IOAPIC_REG_TABLE+1+off, route.dest.upper);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -473,6 +473,14 @@ global irq12
|
|||
global irq13
|
||||
global irq14
|
||||
global irq15
|
||||
global irq16
|
||||
global irq17
|
||||
global irq18
|
||||
global irq19
|
||||
global irq20
|
||||
global irq21
|
||||
global irq22
|
||||
global irq23
|
||||
global apic_timer
|
||||
global apic_lint0
|
||||
global apic_lint1
|
||||
|
|
@ -518,9 +526,9 @@ irq0:
|
|||
; cli
|
||||
push byte 0
|
||||
push byte 32
|
||||
pusha
|
||||
|
||||
Lirq0:
|
||||
pusha
|
||||
push esp
|
||||
call irq_handler
|
||||
add esp, 4
|
||||
|
|
@ -681,13 +689,84 @@ irq15:
|
|||
push byte 47
|
||||
jmp irq_common_stub
|
||||
|
||||
; 48: IRQ16
|
||||
irq16:
|
||||
; irq16 - irq23 are registered as "Interrupt Gate"
|
||||
; Therefore, the interrupt flag (IF) is already cleared.
|
||||
; cli
|
||||
push byte 0
|
||||
push byte 48
|
||||
jmp irq_common_stub
|
||||
|
||||
; 49: IRQ17
|
||||
irq17:
|
||||
; irq16- irq23 are registered as "Interrupt Gate"
|
||||
; Therefore, the interrupt flag (IF) is already cleared.
|
||||
; cli
|
||||
push byte 0
|
||||
push byte 49
|
||||
jmp irq_common_stub
|
||||
|
||||
; 50: IRQ18
|
||||
irq18:
|
||||
; irq16 - irq23 are registered as "Interrupt Gate"
|
||||
; Therefore, the interrupt flag (IF) is already cleared.
|
||||
; cli
|
||||
push byte 0
|
||||
push byte 50
|
||||
jmp irq_common_stub
|
||||
|
||||
; 51: IRQ19
|
||||
irq19:
|
||||
; irq16 - irq23 are registered as "Interrupt Gate"
|
||||
; Therefore, the interrupt flag (IF) is already cleared.
|
||||
; cli
|
||||
push byte 0
|
||||
push byte 51
|
||||
jmp irq_common_stub
|
||||
|
||||
; 52: IRQ20
|
||||
irq20:
|
||||
; irq16- irq23 are registered as "Interrupt Gate"
|
||||
; Therefore, the interrupt flag (IF) is already cleared.
|
||||
; cli
|
||||
push byte 0
|
||||
push byte 52
|
||||
jmp irq_common_stub
|
||||
|
||||
; 53: IRQ21
|
||||
irq21:
|
||||
; irq16 - irq23 are registered as "Interrupt Gate"
|
||||
; Therefore, the interrupt flag (IF) is already cleared.
|
||||
; cli
|
||||
push byte 0
|
||||
push byte 53
|
||||
jmp irq_common_stub
|
||||
|
||||
; 54: IRQ22
|
||||
irq22:
|
||||
; irq16- irq23 are registered as "Interrupt Gate"
|
||||
; Therefore, the interrupt flag (IF) is already cleared.
|
||||
; cli
|
||||
push byte 0
|
||||
push byte 54
|
||||
jmp irq_common_stub
|
||||
|
||||
; 55: IRQ23
|
||||
irq23:
|
||||
; irq16 - irq23 are registered as "Interrupt Gate"
|
||||
; Therefore, the interrupt flag (IF) is already cleared.
|
||||
; cli
|
||||
push byte 0
|
||||
push byte 55
|
||||
jmp irq_common_stub
|
||||
|
||||
apic_timer:
|
||||
; apic timer is registered as "Interrupt Gate"
|
||||
; Therefore, the interrupt flag (IF) is already cleared.
|
||||
; cli
|
||||
push byte 0
|
||||
push byte 48
|
||||
pusha
|
||||
push byte 123
|
||||
; we reuse code of the "traditional" timer interrupt (PIC)
|
||||
jmp Lirq0
|
||||
|
||||
|
|
@ -696,7 +775,7 @@ apic_lint0:
|
|||
; Therefore, the interrupt flag (IF) is already cleared.
|
||||
; cli
|
||||
push byte 0
|
||||
push byte 49
|
||||
push byte 124
|
||||
jmp irq_common_stub
|
||||
|
||||
apic_lint1:
|
||||
|
|
@ -704,7 +783,7 @@ apic_lint1:
|
|||
; Therefore, the interrupt flag (IF) is already cleared.
|
||||
; cli
|
||||
push byte 0
|
||||
push byte 50
|
||||
push byte 125
|
||||
jmp irq_common_stub
|
||||
|
||||
apic_error:
|
||||
|
|
@ -712,7 +791,7 @@ apic_error:
|
|||
; Therefore, the interrupt flag (IF) is already cleared.
|
||||
; cli
|
||||
push byte 0
|
||||
push byte 51
|
||||
push byte 126
|
||||
jmp irq_common_stub
|
||||
|
||||
apic_svr:
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@
|
|||
* This file is part of MetalSVM.
|
||||
*/
|
||||
|
||||
#include <metalsvm/stdio.h>
|
||||
#include <metalsvm/string.h>
|
||||
#include <metalsvm/tasks.h>
|
||||
#include <metalsvm/errno.h>
|
||||
|
|
@ -45,6 +46,14 @@ extern void irq12(void);
|
|||
extern void irq13(void);
|
||||
extern void irq14(void);
|
||||
extern void irq15(void);
|
||||
extern void irq16(void);
|
||||
extern void irq17(void);
|
||||
extern void irq18(void);
|
||||
extern void irq19(void);
|
||||
extern void irq20(void);
|
||||
extern void irq21(void);
|
||||
extern void irq22(void);
|
||||
extern void irq23(void);
|
||||
extern void apic_timer(void);
|
||||
extern void apic_lint0(void);
|
||||
extern void apic_lint1(void);
|
||||
|
|
@ -57,7 +66,7 @@ extern void apic_svr(void);
|
|||
* This array is actually an array of function pointers. We use
|
||||
* this to handle custom IRQ handlers for a given IRQ
|
||||
*/
|
||||
static void *irq_routines[MAX_HANDLERS] = {[0 ... MAX_HANDLERS-1] = NULL };
|
||||
static void* irq_routines[MAX_HANDLERS] = {[0 ... MAX_HANDLERS-1] = NULL };
|
||||
|
||||
/* This installs a custom IRQ handler for the given IRQ */
|
||||
int irq_install_handler(unsigned int irq, irq_handler_t handler)
|
||||
|
|
@ -152,13 +161,30 @@ static int irq_install(void)
|
|||
IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP);
|
||||
|
||||
if (has_apic()) {
|
||||
idt_set_gate(48, (unsigned)apic_timer, KERNEL_CODE_SELECTOR,
|
||||
idt_set_gate(48, (unsigned)irq16, KERNEL_CODE_SELECTOR,
|
||||
IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP);
|
||||
idt_set_gate(49, (unsigned)apic_lint0, KERNEL_CODE_SELECTOR,
|
||||
idt_set_gate(49, (unsigned)irq17, KERNEL_CODE_SELECTOR,
|
||||
IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP);
|
||||
idt_set_gate(50, (unsigned)apic_lint1, KERNEL_CODE_SELECTOR,
|
||||
idt_set_gate(50, (unsigned)irq18, KERNEL_CODE_SELECTOR,
|
||||
IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP);
|
||||
idt_set_gate(51, (unsigned)apic_error, KERNEL_CODE_SELECTOR,
|
||||
idt_set_gate(51, (unsigned)irq19, KERNEL_CODE_SELECTOR,
|
||||
IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP);
|
||||
idt_set_gate(52, (unsigned)irq20, KERNEL_CODE_SELECTOR,
|
||||
IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP);
|
||||
idt_set_gate(53, (unsigned)irq21, KERNEL_CODE_SELECTOR,
|
||||
IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP);
|
||||
idt_set_gate(54, (unsigned)irq22, KERNEL_CODE_SELECTOR,
|
||||
IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP);
|
||||
idt_set_gate(55, (unsigned)irq23, KERNEL_CODE_SELECTOR,
|
||||
IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP);
|
||||
|
||||
idt_set_gate(123, (unsigned)apic_timer, KERNEL_CODE_SELECTOR,
|
||||
IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP);
|
||||
idt_set_gate(124, (unsigned)apic_lint0, KERNEL_CODE_SELECTOR,
|
||||
IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP);
|
||||
idt_set_gate(125, (unsigned)apic_lint1, KERNEL_CODE_SELECTOR,
|
||||
IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP);
|
||||
idt_set_gate(126, (unsigned)apic_error, KERNEL_CODE_SELECTOR,
|
||||
IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP);
|
||||
idt_set_gate(127, (unsigned)apic_svr, KERNEL_CODE_SELECTOR,
|
||||
IDT_FLAG_PRESENT|IDT_FLAG_RING0|IDT_FLAG_32BIT|IDT_FLAG_INTTRAP);
|
||||
|
|
@ -196,16 +222,10 @@ void irq_handler(struct state *s)
|
|||
/* This is a blank function pointer */
|
||||
void (*handler) (struct state * s);
|
||||
|
||||
if (s->int_no - 32 > MAX_HANDLERS) {
|
||||
apic_eoi();
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* Find out if we have a custom handler to run for this
|
||||
* IRQ and then finally, run it
|
||||
*/
|
||||
|
||||
*/
|
||||
handler = irq_routines[s->int_no - 32];
|
||||
if (handler)
|
||||
handler(s);
|
||||
|
|
@ -214,7 +234,7 @@ void irq_handler(struct state *s)
|
|||
* If the IDT entry that was invoked was greater-than-or-equal to 48,
|
||||
* then we use the APIC
|
||||
*/
|
||||
if (s->int_no >= 48) {
|
||||
if (apic_is_enabled() || s->int_no >= 123) {
|
||||
apic_eoi();
|
||||
return;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -173,7 +173,7 @@ void fault_handler(struct state *s)
|
|||
kputs(" Exception.\n");
|
||||
|
||||
/* Now, we signalize that we have handled the interrupt */
|
||||
if (has_apic())
|
||||
if (apic_is_enabled())
|
||||
apic_eoi();
|
||||
else
|
||||
outportb(0x20, 0x20);
|
||||
|
|
|
|||
|
|
@ -81,11 +81,11 @@ int timer_init(void)
|
|||
uint64_t start;
|
||||
|
||||
/*
|
||||
* Installs 'timer_handler' for the PIC (0) and APIC timer (16),
|
||||
* Installs 'timer_handler' for the PIC and APIC timer,
|
||||
* only one handler will be later used.
|
||||
*/
|
||||
irq_install_handler(0, timer_handler);
|
||||
irq_install_handler(16, timer_handler);
|
||||
irq_install_handler(123-32, timer_handler);
|
||||
|
||||
/*
|
||||
* The Rock Creek processor doesn't posseess an tradional PIC.
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue