add first functional version of the eMAC driver
- this driver required at least sccKit 1.4.0
This commit is contained in:
Stefan Lankes
parent
19fffd46c5
commit
f8be2e3483
3 changed files with 238 additions and 198 deletions
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@ -735,7 +735,7 @@ int arch_paging_init(void)
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kprintf("Map message passing buffers at 0x%x\n", viraddr);
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// map the FPGA registers
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viraddr = map_region(FPGA_BASE, FPGA_BASE, (16*1024*1024) >> PAGE_SHIFT, MAP_KERNEL_SPACE|MAP_NO_CACHE);
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viraddr = map_region(FPGA_BASE, FPGA_BASE, 0x10000 >> PAGE_SHIFT, MAP_KERNEL_SPACE|MAP_NO_CACHE);
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kprintf("Map FPGA regsiters at 0x%x\n", viraddr);
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#endif
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@ -17,6 +17,12 @@
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* This file is part of MetalSVM.
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*/
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/*
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* This eMAC driver required at least sccKit 1.4.0 and based on
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* the eMAC Driver Description (section 9.6.5) in the
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* SccKit 1.4.0 User’s Guide (Revision 0.92 Part 9).
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*/
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#include <metalsvm/stddef.h>
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#include <metalsvm/stdio.h>
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#include <metalsvm/string.h>
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@ -50,7 +56,7 @@
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#define EMAC_RX_CONTROL 0x9000
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#define EMAC_TX_CONTROL 0x9900
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/* Xilinx IP configuration - offsets */
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/* IP configuration - offsets */
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#define CONFIG_FLOW_CONTROL_ADD 0xC0
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#define TRANSMITTER_ADDRESS 0x80
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#define RECEIVER1_ADDRESS 0x40
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@ -94,18 +100,30 @@
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#define CLINE_ALIGN(_x) (((_x) + CLINE_SIZE - 1) & CLINE_MASK)
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#define CLINE_PACKETS(_x) (CLINE_ALIGN(_x) >> CLINE_SHIFT)
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/* Flush */
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#define CL1FLUSH __asm__ volatile (".byte 0x0F; .byte 0x0A;\n")
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/* Read 16bit from buffer */
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#define U16(_addr) (256 * (*((uint8_t*) (_addr + 1))) + (*((uint8_t*)(_addr))))
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#define MAC_ADDRESS 0x00454D414331ULL
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#define MAC_HI(_x) ((((_x) >> 32)) & 0xFFFF)
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#define MAC_LO(_x) (((_x) ) & 0xFFFFFFFF)
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static struct netif* mynetif[4] = {NULL, NULL, NULL, NULL};
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static struct netif* mynetif;
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static inline int read_emac(int num_emac, int offset, int core)
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static int read_emac(int num_emac, int offset, int core)
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{
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return *((volatile int*) (FPGA_BASE + num_emac * 0x1000 + offset + core * 4));
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int ret;
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ret = *((volatile int*) (FPGA_BASE + num_emac * 0x1000 + offset + core * 4));
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/* no error: read twice, as xilinx ip need some time... */
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ret = *((volatile int*) (FPGA_BASE + num_emac * 0x1000 + offset + core * 4));
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return ret;
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}
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static inline void write_emac(int num_emac, int offset, int core, int value)
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static void write_emac(int num_emac, int offset, int core, int value)
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{
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*((volatile int*) (FPGA_BASE + num_emac * 0x1000 + offset + core * 4)) = value;
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}
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@ -121,14 +139,14 @@ static err_t rckemacif_output(struct netif* netif, struct pbuf* p)
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rckemacif_t* rckemacif = netif->state;
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uint32_t i;
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struct pbuf *q;
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void *addr = NULL;
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uint16_t read_offset = 0;
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int rest = 0;
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int packets = 0;
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void *addr;
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uint16_t read_offset;
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int rest;
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int packets;
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int sum = 0;
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/* check for over/underflow */
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if (BUILTIN_EXPECT(p->tot_len > 1536, 0)) {
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if (BUILTIN_EXPECT((p->tot_len < 20) || (p->tot_len > 1536), 0)) {
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LWIP_DEBUGF(NETIF_DEBUG, ("rckemacif_output: illegal packet length %d => drop\n", p->len));
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return ERR_IF;
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}
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@ -170,8 +188,8 @@ again:
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* q traverses through linked list of pbuf's
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* This list MUST consist of a single packet ONLY
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*/
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for (q = p, i = 0; q != 0; q = q->next) {
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memcpy(addr + 2 + i, q->payload, q->len);
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for (q=p, i=0; q!=0; q=q->next) {
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memcpy(((uint8_t*)addr) + 2 + i, q->payload, q->len);
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i += q->len;
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}
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@ -193,7 +211,7 @@ again:
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q = p; i = 0;
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while ((q != 0) && (i < bytes_to_copy)) {
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sz = q->len > bytes_to_copy-i ? bytes_to_copy-i : q->len;
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memcpy(addr + 2 + i, q->payload, sz);
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memcpy(((uint8_t*) addr) + 2 + i, q->payload, sz);
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bytes_left -= sz;
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i += sz;
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if (i < bytes_to_copy)
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@ -207,12 +225,12 @@ again:
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i = 0;
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if (sz < q->len) {
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memcpy(addr, q->payload + sz, q->len - sz);
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memcpy((uint8_t*) addr, q->payload + sz, q->len - sz);
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bytes_left -= (q->len - sz);
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i = q->len - sz;
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}
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for(q=q->next; (q != 0); q = q->next) {
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memcpy(addr+i, q->payload, q->len);
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memcpy(((uint8_t*) addr) + i, q->payload, q->len);
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i += q->len;
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}
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@ -228,8 +246,7 @@ again:
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*((volatile int*) rckemacif->tx_buffer) = 2;
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/* set new write offset */
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LWIP_DEBUGF(NETIF_DEBUG, ("Update tx write offset: %d (read offset %d)\n", rckemacif->tx_write_offset, read_offset));
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//LWIP_DEBUGF(NETIF_DEBUG, ("Update tx write offset: %d (read offset %d)\n", rckemacif->tx_write_offset, read_offset));
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write_emac(rckemacif->num_emac, EMAC_TX_CONTROL+EMAC_TX_BUFFER_WRITE_OFFSET, rckemacif->core, rckemacif->tx_write_offset);
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#if ETH_PAD_SIZE
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@ -241,151 +258,177 @@ again:
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return ERR_OK;
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}
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#if 0
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static void rtl_rx_inthandler(struct netif* netif)
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static void rckemacif_rx_handler(struct netif* netif, unsigned int write_offset)
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{
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rtl1839if_t* rtl8139if = netif->state;
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uint16_t header;
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uint16_t length, i;
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uint8_t cmd;
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struct pbuf *p = NULL;
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rckemacif_t* rckemacif = netif->state;
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unsigned short read_offset;
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unsigned int counter;
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volatile void *addr;
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uint16_t i, length;
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struct pbuf *p;
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struct pbuf* q;
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cmd = inportb(rtl8139if->iobase + CR);
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while(!(cmd & CR_BUFE)) {
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header = *((uint16_t*) (rtl8139if->rx_buffer+rtl8139if->rx_pos));
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rtl8139if->rx_pos = (rtl8139if->rx_pos + 2) % (8192+16);
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if (write_offset > rckemacif->rx_buffer_max) {
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LWIP_DEBUGF(NETIF_DEBUG, ("Warning, write offset > buffer max!! (%d > %d)\n", write_offset, rckemacif->rx_buffer_max));
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read_offset = 1;
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write_emac(rckemacif->num_emac, EMAC_RX_CONTROL + EMAC_RX_BUFFER_READ_OFFSET, rckemacif->core, read_offset);
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rckemacif->rx_read_offset = read_offset;
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return;
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}
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while(1) {
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if ((write_offset != 0) && (rckemacif->rx_read_offset != write_offset)) {
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read_offset = rckemacif->rx_read_offset;
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read_offset++;
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if (read_offset < 1 || read_offset > rckemacif->rx_buffer_max) {
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read_offset = 1;
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}
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addr = rckemacif->rx_buffer + read_offset * 32;
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length = U16(addr);
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// Check for over/underflow
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if ((length < 20) || (length > 1536)) {
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LWIP_DEBUGF(NETIF_DEBUG, ("rckemacif_rx_handler(): illegal packet length %d => drop\n", length));
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LWIP_DEBUGF(NETIF_DEBUG, ("start read at %d; write_offset at %d; addr: %p, packet len: %d\n", read_offset, write_offset, addr, length));
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read_offset = write_offset;
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#if 1
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kprintf("Buffer:\n");
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for (i = 0; i < 32; i++) {
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kprintf("%2.2x ", ((char*)addr)[i] & 0xFF);
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}
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kprintf("\n");
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kprintf("Buffer0:\n");
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for (i = 0; i < 32; i++) {
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kprintf("%2.2x ", ((char*)rckemacif->rx_buffer)[i] & 0xFF);
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}
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kprintf("\n");
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#endif
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LINK_STATS_INC(link.memerr);
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LINK_STATS_INC(link.drop);
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goto rxDone;
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}
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if (header & ISR_ROK) {
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length = *((uint16_t*) (rtl8139if->rx_buffer+rtl8139if->rx_pos)) - 4; // copy packet (but not the CRC)
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rtl8139if->rx_pos = (rtl8139if->rx_pos + 2) % (8192+16);
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#if ETH_PAD_SIZE
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length += ETH_PAD_SIZE; /* allow room for Ethernet padding */
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#endif
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//LWIP_DEBUGF(NETIF_DEBUG, ("length %u, read_offset %u, write_offset %u\n", length, read_offset, write_offset));
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p = pbuf_alloc(PBUF_RAW, length, PBUF_POOL);
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if (p) {
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#if ETH_PAD_SIZE
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pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */
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#endif
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for (q=p; q!=NULL; q=q->next) {
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for(i=0; i<q->len; i++) {
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((uint8_t*) q->payload)[i] = rtl8139if->rx_buffer[rtl8139if->rx_pos];
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rtl8139if->rx_pos = (rtl8139if->rx_pos + 1) % (8192+16);
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}
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}
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if (read_offset < write_offset) {
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for (q=p, counter=0; q!=NULL; q=q->next) {
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for(i=0; i<q->len; i++, counter++) {
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((uint8_t*) q->payload)[i] = ((uint8_t*)addr)[2 + counter];
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}
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}
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read_offset += CLINE_PACKETS(p->len + 2) - 1;
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} else {
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int rest;
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int bytesLeft = length;
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int bytesToCopy = length;
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/* rest to the end of buffer - 2 bytes length information */
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rest = (rckemacif->rx_buffer_max - read_offset + 1) * 32 - 2;
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if (length > rest)
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bytesToCopy = rest;
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LWIP_DEBUGF(NETIF_DEBUG, ("bytes to copy: %d, bytesLeft: %d\n", bytesToCopy, bytesLeft));
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for (q=p, counter=0; q!=NULL; q=q->next) {
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for(i=0; i<q->len; i++, counter++) {
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if (counter < bytesToCopy)
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((uint8_t*) q->payload)[i] = ((uint8_t*)addr)[2 + counter];
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else
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goto out;
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}
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}
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out:
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bytesLeft -= bytesToCopy;
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if (bytesLeft != 0) {
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addr = rckemacif->rx_buffer + 0x20;
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LWIP_DEBUGF(NETIF_DEBUG, ("copying from %p, left: %d (%x)\n", addr, bytesLeft, ((uint8_t*)addr)[0]));
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for(counter=0; (i<q->len) && (counter < bytesLeft); i++, counter++)
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((uint8_t*) q->payload)[i] = ((uint8_t*)addr)[counter];
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for(q=q->next; (q!=NULL) && (counter < bytesLeft); q=q->next) {
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for(i=0; (i<q->len) && (counter < bytesLeft); i++, counter++) {
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((uint8_t*) q->payload)[i] = ((uint8_t*)addr)[counter];
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}
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}
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read_offset = CLINE_PACKETS(bytesLeft);
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} else {
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read_offset += CLINE_PACKETS(p->len + 2) - 1;
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}
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}
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#if ETH_PAD_SIZE
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pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */
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#endif
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mailbox_ptr_post(&rtl8139if->mbox, (void*)p);
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//rtl8139if_input(netif, p);
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mailbox_ptr_post(&rckemacif->mbox, (void*)p);
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LINK_STATS_INC(link.recv);
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} else {
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LWIP_DEBUGF(NETIF_DEBUG, ("rtl8139if_rx_inthandler: not enough memory!\n"));
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rtl8139if->rx_pos += (rtl8139if->rx_pos + length) % (8192+16);
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LWIP_DEBUGF(NETIF_DEBUG, ("rckemacif_rx_inthandler: not enough memory!\n"));
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LINK_STATS_INC(link.memerr);
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LINK_STATS_INC(link.drop);
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}
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// packets are dword aligned
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rtl8139if->rx_pos = ((rtl8139if->rx_pos + 4 + 3) & ~0x3) % (8192+16);
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outportw(rtl8139if->iobase + CAPR, rtl8139if->rx_pos - 0x10);
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} else {
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LWIP_DEBUGF(NETIF_DEBUG, ("rtl8139if_rx_inthandler: invalid header!\n"));
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LINK_STATS_INC(link.memerr);
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LINK_STATS_INC(link.drop);
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break;
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}
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cmd = inportb(rtl8139if->iobase + CR);
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rxDone:
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/* set new read pointer */
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//LWIP_DEBUGF(NETIF_DEBUG, ("Update rx read offset: %d\n", read_offset));
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write_emac(rckemacif->num_emac, EMAC_RX_CONTROL + EMAC_RX_BUFFER_READ_OFFSET, rckemacif->core, read_offset);
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rckemacif->rx_read_offset = read_offset;
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} else break;
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}
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}
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static void rtl_tx_inthandler(struct netif* netif)
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{
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rtl1839if_t* rtl8139if = netif->state;
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uint32_t checks = rtl8139if->tx_queue - rtl8139if->tx_complete;
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uint32_t txstatus;
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uint8_t tmp8;
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while(checks > 0)
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{
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tmp8 = rtl8139if->tx_complete % 4;
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txstatus = inportl(rtl8139if->iobase + TSD0 + tmp8 * 4);
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if (!(txstatus & (TSD_TOK|TSD_TUN|TSD_TABT)))
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return;
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if (txstatus & (TSD_TABT | TSD_OWC)) {
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LWIP_DEBUGF(NETIF_DEBUG, ("rtl8139_tx_inthandler: major error\n"));
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continue;
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}
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if (txstatus & TSD_TUN) {
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LWIP_DEBUGF(NETIF_DEBUG, ("rtl8139_tx_inthandler: transmit underrun\n"));
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}
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if (txstatus & TSD_TOK) {
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rtl8139if->tx_inuse[tmp8] = 0;
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rtl8139if->tx_complete++;
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checks--;
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}
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}
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}
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#endif
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static void rckemacif_handler(struct state* s)
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{
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LWIP_DEBUGF(NETIF_DEBUG, ("HELLO! Got interrupt!\n"));
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unsigned int status, tmp;
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unsigned int write_offset;
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rckemacif_t* rckemacif = mynetif->state;
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#if 0
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rtl1839if_t* rtl8139if = mynetif->state;
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uint16_t isr_contents;
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while (1) {
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isr_contents = inportw(rtl8139if->iobase + ISR);
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if (isr_contents == 0)
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break;
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if (isr_contents & ISR_ROK) {
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rtl_rx_inthandler(mynetif);
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outportw(rtl8139if->iobase + ISR, ISR_ROK);
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}
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if (isr_contents & ISR_TOK) {
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rtl_tx_inthandler(mynetif);
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outportw(rtl8139if->iobase + ISR, ISR_TOK);
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}
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if (isr_contents & ISR_RER) {
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LWIP_DEBUGF(NETIF_DEBUG, ("rtl8139if_handler: RX error detected!\n"));
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outportw(rtl8139if->iobase + ISR, ISR_RER);
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}
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if (isr_contents & ISR_TER) {
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LWIP_DEBUGF(NETIF_DEBUG, ("rtl8139if_handler: TX error detected!\n"));
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outportw(rtl8139if->iobase + ISR, ISR_TER);
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}
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if (isr_contents & ISR_RXOVW) {
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LWIP_DEBUGF(NETIF_DEBUG, ("rtl8139if_handler: RX overflow detected!\n"));
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outportw(rtl8139if->iobase + ISR, ISR_RXOVW);
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}
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status = *((volatile int*) (FPGA_BASE + IRQ_STATUS + rckemacif->core * 2 * 4));
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// read twice to be sure
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status = *((volatile int*) (FPGA_BASE + IRQ_STATUS + rckemacif->core * 2 * 4));
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if (!(status & (1 << rckemacif->num_emac))) {
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LWIP_DEBUGF(NETIF_DEBUG, ("rckemacif_handler: no interrupt\n"));
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return;
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}
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#endif
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nexttry:
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/* check for updated write offset */
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CL1FLUSH;
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write_offset = *((volatile unsigned int*) (rckemacif->rx_buffer)) & 0xFFFF;
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//write_offset = read_emac(rckemacif->num_emac, EMAC_RX_CONTROL + EMAC_RX_BUFFER_WRITE_OFFSET, rckemacif->core);
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if ((write_offset != 0) && (rckemacif->rx_read_offset != write_offset)) {
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rckemacif_rx_handler(mynetif, write_offset);
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goto nexttry;
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}
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/* Set interrupt bit */
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tmp = *((volatile unsigned int*) rckemacif->irq_address);
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tmp &= ~(EMAC_IRQ_MASK);
|
||||
*((volatile unsigned int*) rckemacif->irq_address) = tmp;
|
||||
|
||||
/* Reset */
|
||||
*((volatile unsigned*) (FPGA_BASE + IRQ_RESET + rckemacif->core * 2 * 4)) = (1 << rckemacif->num_emac);
|
||||
}
|
||||
|
||||
err_t rckemacif_wait(struct netif* netif, uint32_t poll)
|
||||
{
|
||||
return ERR_OK;
|
||||
#if 0
|
||||
rckemacif_t* rckemacif = netif->state;
|
||||
struct eth_hdr *ethhdr;
|
||||
struct pbuf *p = NULL;
|
||||
err_t err = ERR_OK;
|
||||
|
||||
LWIP_DEBUGF(NETIF_DEBUG, ("Hello from rckemacif_wait!\n"));
|
||||
|
||||
if (poll) {
|
||||
if (mailbox_ptr_tryfetch(&(rckemacif->mbox), (void**) &p))
|
||||
return err;
|
||||
|
|
@ -396,6 +439,8 @@ err_t rckemacif_wait(struct netif* netif, uint32_t poll)
|
|||
/* points to packet payload, which starts with an Ethernet header */
|
||||
ethhdr = p->payload;
|
||||
|
||||
//LWIP_DEBUGF(NETIF_DEBUG, ("Got packet of type 0x%x!\n", htons(ethhdr->type)));
|
||||
|
||||
switch (htons(ethhdr->type)) {
|
||||
/* IP or ARP packet? */
|
||||
case ETHTYPE_ARP:
|
||||
|
|
@ -406,7 +451,7 @@ err_t rckemacif_wait(struct netif* netif, uint32_t poll)
|
|||
case ETHTYPE_PPPOE:
|
||||
#endif /* PPPOE_SUPPORT */
|
||||
/* full packet send to tcpip_thread to process */
|
||||
if ((err = mynetif[netif->num]->input(p, mynetif[netif->num])) != ERR_OK) {
|
||||
if ((err = mynetif->input(p, mynetif)) != ERR_OK) {
|
||||
LWIP_DEBUGF(NETIF_DEBUG, ("rckemacif_poll: IP input error\n"));
|
||||
pbuf_free(p);
|
||||
}
|
||||
|
|
@ -417,21 +462,20 @@ err_t rckemacif_wait(struct netif* netif, uint32_t poll)
|
|||
}
|
||||
|
||||
return err;
|
||||
#endif
|
||||
}
|
||||
|
||||
err_t rckemacif_init(struct netif* netif)
|
||||
{
|
||||
rckemacif_t* rckemacif;
|
||||
int num, num_emac;
|
||||
int num_emac;
|
||||
int macPorts;
|
||||
int i, tmp, x, y, z, core;
|
||||
uint64_t tile_offset;
|
||||
uint16_t write_offset = 0;
|
||||
uint16_t read_offset = 0;
|
||||
int mode = 0;
|
||||
int subdest = 0;
|
||||
int route = 0;
|
||||
uint16_t write_offset;
|
||||
uint16_t read_offset;
|
||||
int mode;
|
||||
int subdest;
|
||||
int route;
|
||||
|
||||
LWIP_ASSERT("netif != NULL", (netif != NULL));
|
||||
|
||||
|
|
@ -457,7 +501,8 @@ err_t rckemacif_init(struct netif* netif)
|
|||
kfree(rckemacif, sizeof(rckemacif_t));
|
||||
return ERR_MEM;
|
||||
}
|
||||
memset(rckemacif->rx_buffer, 0, BUFFER_SIZE);
|
||||
memset(rckemacif->rx_buffer, 0x00, 0x20);
|
||||
memset(rckemacif->rx_buffer + 0x20, 0xDA, BUFFER_SIZE - 0x20);
|
||||
rckemacif->rx_buffer_max = CLINE_PACKETS(BUFFER_SIZE) - 1;
|
||||
|
||||
/* allocate the send buffers */
|
||||
|
|
@ -468,7 +513,8 @@ err_t rckemacif_init(struct netif* netif)
|
|||
kfree(rckemacif, sizeof(rckemacif_t));
|
||||
return ERR_MEM;
|
||||
}
|
||||
memset(rckemacif->tx_buffer, 0, BUFFER_SIZE);
|
||||
memset(rckemacif->tx_buffer, 0x00, 0x20);
|
||||
memset(rckemacif->tx_buffer + 0x20, 0xDA, BUFFER_SIZE - 0x20);
|
||||
rckemacif->tx_buffer_max = CLINE_PACKETS(BUFFER_SIZE) - 1;
|
||||
|
||||
mailbox_ptr_init(&rckemacif->mbox);
|
||||
|
|
@ -478,42 +524,42 @@ err_t rckemacif_init(struct netif* netif)
|
|||
* (offset, subdest, route)
|
||||
*/
|
||||
if (z == 0) {
|
||||
tmp = ReadConfigReg(CRB_OWN + GLCFG0);
|
||||
rckemacif->irq_address = CRB_OWN + GLCFG0;
|
||||
tmp = ReadConfigReg(CRB_OWN + LUT0);
|
||||
rckemacif->irq_address = (void*) (CRB_OWN + GLCFG0);
|
||||
} else {
|
||||
tmp = ReadConfigReg(CRB_OWN + GLCFG1);
|
||||
rckemacif->irq_address = CRB_OWN + GLCFG1;
|
||||
tmp = ReadConfigReg(CRB_OWN + LUT1);
|
||||
rckemacif->irq_address = (void*) (CRB_OWN + GLCFG1);
|
||||
}
|
||||
tile_offset = (unsigned long long)((unsigned long long) tmp & 0x3FF) << 24;
|
||||
tile_offset = (uint64_t)((uint64_t) tmp & 0x3FF) << 24;
|
||||
subdest = (tmp >> 10) & 0x07;
|
||||
route = (tmp >> 13) & 0xFF;
|
||||
mode = (subdest << 8) + route;
|
||||
LWIP_DEBUGF(NETIF_DEBUG, ("tile_offset = 0x%llx\n", tile_offset));
|
||||
|
||||
/* get fpga/sccKit port settings */
|
||||
tmp = *((volatile int*)(FPGA_BASE + 0x822C));
|
||||
tmp = *((volatile int*)(FPGA_BASE + 0x822C));
|
||||
macPorts = ((tmp >> 9 ) & 0xFF);
|
||||
|
||||
LWIP_DEBUGF(NETIF_DEBUG, ("rckemacif_init: eMAC0: %s eMAC1: %s eMAC2: %s eMAC3: %s\n",
|
||||
(macPorts & EMAC0) != 0 ? "present" : "-",
|
||||
(macPorts & EMAC1) != 0 ? "present" : "-",
|
||||
(macPorts & EMAC2) != 0 ? "present" : "-",
|
||||
(macPorts & EMAC3) != 0 ? "present" : "-"));
|
||||
LWIP_DEBUGF(NETIF_DEBUG, ("rckemacif_init: eMAC0: %s eMAC1: %s eMAC2: %s eMAC3: %s\n",
|
||||
(macPorts & EMAC0) != 0 ? "present" : "-",
|
||||
(macPorts & EMAC1) != 0 ? "present" : "-",
|
||||
(macPorts & EMAC2) != 0 ? "present" : "-",
|
||||
(macPorts & EMAC3) != 0 ? "present" : "-"));
|
||||
|
||||
// determine device and emac number
|
||||
for(num=0; (num<4) && (mynetif[num] != NULL); num++)
|
||||
;
|
||||
if (num >= 4)
|
||||
return ERR_ARG;
|
||||
for(i=0, num_emac=0; (i<=num) && (num_emac < 4); i++) {
|
||||
while (((macPorts & (1 << num_emac)) == 0) && (num_emac < 4))
|
||||
num_emac++;
|
||||
}
|
||||
num_emac=0;
|
||||
while (((macPorts & (1 << num_emac)) == 0) && (num_emac < 4))
|
||||
num_emac++;
|
||||
if (num_emac >= 4)
|
||||
return ERR_ARG;
|
||||
mynetif[num] = netif;
|
||||
mynetif = netif;
|
||||
rckemacif->num_emac = num_emac;
|
||||
|
||||
LWIP_DEBUGF(NETIF_DEBUG, ("rckemacif_init: map device %d to eMAC %d\n", num, num_emac));
|
||||
LWIP_DEBUGF(NETIF_DEBUG, ("rckemacif_init: used eMAC device %d\n", num_emac));
|
||||
|
||||
tmp = read_emac(num_emac, EMAC_IPCONF+TRANSMITTER_ADDRESS, 0);
|
||||
tmp = read_emac(num_emac, EMAC_IPCONF+RECEIVER1_ADDRESS, 0);
|
||||
|
||||
if (core == 0) {
|
||||
/* Only core 0 initialize the xilinx port */
|
||||
|
|
@ -524,23 +570,23 @@ err_t rckemacif_init(struct netif* netif)
|
|||
int add_filter_mod = 0;
|
||||
|
||||
/* Disable tx and rx flow control of eMAC */
|
||||
LWIP_DEBUGF(NETIF_DEBUG, ("Disabling tx/rx flow control of eMAC%d\n", num_emac));
|
||||
flow_control = read_emac(num_emac, EMAC_IPCONF+CONFIG_FLOW_CONTROL_ADD, 0);
|
||||
LWIP_DEBUGF(NETIF_DEBUG, ("Disabling tx/rx flow control of eMAC%d\n", num_emac));
|
||||
flow_control = read_emac(num_emac, EMAC_IPCONF+CONFIG_FLOW_CONTROL_ADD, 0);
|
||||
|
||||
/* Set top 3 bits of the flow control configuration to zero,
|
||||
* therefore disabling tx and rx flow control
|
||||
*/
|
||||
flow_control &= 0x7FFFFFF;
|
||||
write_emac(num_emac, EMAC_IPCONF+CONFIG_FLOW_CONTROL_ADD, 0, flow_control);
|
||||
write_emac(num_emac, EMAC_IPCONF+CONFIG_FLOW_CONTROL_ADD, 0, flow_control);
|
||||
|
||||
/* Sanity check */
|
||||
flow_control = read_emac(num_emac, EMAC_IPCONF+CONFIG_FLOW_CONTROL_ADD, 0);
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" CONFIG_FLOW_CONTROL_ADD set: 0x%x\n", flow_control));
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" CONFIG_FLOW_CONTROL_ADD set: 0x%x\n", flow_control));
|
||||
|
||||
/* Setting the tx configuration bit to enable the transmitter and
|
||||
* set to full duplex mode.
|
||||
*/
|
||||
LWIP_DEBUGF(NETIF_DEBUG, ("Setting rx configuration of eMAC%d\n", num_emac));
|
||||
LWIP_DEBUGF(NETIF_DEBUG, ("Setting rx configuration of eMAC%d\n", num_emac));
|
||||
transmitter_addr = read_emac(num_emac, EMAC_IPCONF+TRANSMITTER_ADDRESS, 0);
|
||||
|
||||
/* Now set the relevant bits and write back into the register:
|
||||
|
|
@ -552,7 +598,7 @@ err_t rckemacif_init(struct netif* netif)
|
|||
write_emac(num_emac, EMAC_IPCONF+TRANSMITTER_ADDRESS, 0, transmitter_addr);
|
||||
|
||||
transmitter_addr = read_emac(num_emac, EMAC_IPCONF+TRANSMITTER_ADDRESS, 0);
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" TRANSMITTER_ADDRESS set: %x\n", transmitter_addr));
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" TRANSMITTER_ADDRESS set: %x\n", transmitter_addr));
|
||||
|
||||
/* Setting the rx configuration bit to enable the transmitter and
|
||||
* set to full duplex mode.
|
||||
|
|
@ -602,32 +648,29 @@ err_t rckemacif_init(struct netif* netif)
|
|||
* 31 (promiscuous mode) = 1 not working, but thats ok!
|
||||
*/
|
||||
add_filter_mod |= (1 << 31);
|
||||
write_emac(num_emac, EMAC_IPCONF+ADD_FILTER_MOD, 0, add_filter_mod);
|
||||
write_emac(num_emac, EMAC_IPCONF+ADD_FILTER_MOD, 0, add_filter_mod);
|
||||
|
||||
add_filter_mod = read_emac(num_emac, EMAC_IPCONF+ADD_FILTER_MOD, 0);
|
||||
add_filter_mod = read_emac(num_emac, EMAC_IPCONF+ADD_FILTER_MOD, 0);
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" ADD_FILTER_MOD set: %x\n", add_filter_mod));
|
||||
}
|
||||
|
||||
sleep(3);
|
||||
|
||||
/* Start address */
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" RX Buffer %p (%lx phys)\n", rckemacif->rx_buffer, virt_to_phys(rckemacif->rx_buffer)));
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" RX Buffer %p (%lx phys)\n", rckemacif->rx_buffer, virt_to_phys((uint32_t)rckemacif->rx_buffer)));
|
||||
|
||||
/**** Receiver configuration ****/
|
||||
|
||||
uint32_t utmp = virt_to_phys(rckemacif->rx_buffer);
|
||||
uint32_t addr_offset = tile_offset + utmp;
|
||||
addr_offset >>= 5;
|
||||
write_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_BUFFER_START_ADDRESS, core, addr_offset);
|
||||
utmp = read_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_BUFFER_START_ADDRESS, core);
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" RX Buffer set to @%x\n", utmp));
|
||||
uint64_t addr_offset = (tile_offset + (uint64_t) virt_to_phys((uint32_t) rckemacif->rx_buffer)) >> 5;
|
||||
write_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_BUFFER_START_ADDRESS, core, (uint32_t) addr_offset);
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" RX Buffer set to @%x\n", read_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_BUFFER_START_ADDRESS, core)));
|
||||
|
||||
/* Set buffer write offset */
|
||||
/* Get buffer write offset */
|
||||
write_offset = read_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_BUFFER_WRITE_OFFSET, core);
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" RX Buffer write offset at: %d\n", write_offset));
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" RX Buffer write offset at: %d\n", write_offset));
|
||||
|
||||
/* Set buffer read offset to write offset */
|
||||
write_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_BUFFER_READ_OFFSET, core, write_offset);
|
||||
write_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_BUFFER_READ_OFFSET, core, write_offset);
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" RX Buffer read offset set to: %d\n", read_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_BUFFER_READ_OFFSET, core)));
|
||||
rckemacif->rx_read_offset = write_offset;
|
||||
|
||||
|
|
@ -637,49 +680,46 @@ err_t rckemacif_init(struct netif* netif)
|
|||
|
||||
/* Threshold */
|
||||
write_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_BUFFER_THRESHOLD, core, 0x01);
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" RX Threshold set to %x\n", read_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_BUFFER_THRESHOLD, core)));
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" RX Threshold set to %x\n", read_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_BUFFER_THRESHOLD, core)));
|
||||
|
||||
/* Route */
|
||||
write_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_MODE, core, (core << 24) | (((y << 4) | x) << 16) | mode);
|
||||
write_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_MODE, core, (z << 24) | (((y << 4) | x) << 16) | mode);
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" RX Mode set to %x\n", read_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_MODE, core)));
|
||||
|
||||
// determine mac address
|
||||
uint32_t mac1 = *((uint32_t*)(FPGA_BASE+0x7E00));
|
||||
uint32_t mac2 = *((uint32_t*)(FPGA_BASE+0x7E04));
|
||||
uint64_t mac = (((unsigned long long)mac1) << 32) + ( unsigned long long ) mac2;
|
||||
uint32_t mac1 = *((volatile uint32_t*)(FPGA_BASE+0x7E00));
|
||||
uint32_t mac2 = *((volatile uint32_t*)(FPGA_BASE+0x7E04));
|
||||
uint64_t mac = (((unsigned long long)mac1) << 32) + (unsigned long long) mac2;
|
||||
if (mac == 0x00)
|
||||
mac = MAC_ADDRESS;
|
||||
/* Calculate mac address of core depending on selected emac device */
|
||||
mac = mac + (1 << num_emac) * 0x100 + core;
|
||||
|
||||
for (i=0; i<6; i++)
|
||||
mynetif->hwaddr[5-i] = (mac >> (i*8)) & 0xFF;
|
||||
LWIP_DEBUGF(NETIF_DEBUG, ("rckemacif_init: MAC address "));
|
||||
for (i=0; i<6; i++) {
|
||||
mynetif[num]->hwaddr[i] = mac & 0xFF;
|
||||
mac = mac >> 8;
|
||||
LWIP_DEBUGF(NETIF_DEBUG, ("%02x ", mynetif[num]->hwaddr[i]));
|
||||
}
|
||||
for (i=0; i<6; i++)
|
||||
LWIP_DEBUGF(NETIF_DEBUG, ("%02x ", mynetif->hwaddr[i]));
|
||||
LWIP_DEBUGF(NETIF_DEBUG, ("\n"));
|
||||
|
||||
write_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_NETWORK_PORT_MAC_ADDRESS_HI, core, MAC_HI(mac));
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" MAC1 set to %x\n", read_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_NETWORK_PORT_MAC_ADDRESS_HI, core)));
|
||||
write_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_NETWORK_PORT_MAC_ADDRESS_LO, core, MAC_LO(mac));
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" MAC2 set to %x\n", read_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_NETWORK_PORT_MAC_ADDRESS_LO, core)));
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" MAC1 set to %x\n", read_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_NETWORK_PORT_MAC_ADDRESS_HI, core)));
|
||||
write_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_NETWORK_PORT_MAC_ADDRESS_LO, core, MAC_LO(mac));
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" MAC2 set to %x\n", read_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_NETWORK_PORT_MAC_ADDRESS_LO, core)));
|
||||
|
||||
/* Activate network port by setting enable bit */
|
||||
write_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_NETWORK_PORT_ENABLE, core, 0x01);
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" RX Port enable set to %x\n", read_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_NETWORK_PORT_ENABLE, core)));
|
||||
/* Activate network port by setting enable bit */
|
||||
write_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_NETWORK_PORT_ENABLE, core, 0x01);
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" RX Port enable set to %x\n", read_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_NETWORK_PORT_ENABLE, core)));
|
||||
|
||||
/**** Transfer configuration ****/
|
||||
|
||||
/* Start address */
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" TX Buffer %p (%lx phys)\n", rckemacif->tx_buffer, virt_to_phys(rckemacif->tx_buffer)));
|
||||
utmp = virt_to_phys(rckemacif->tx_buffer);
|
||||
write_emac(num_emac, EMAC_TX_CONTROL + EMAC_TX_BUFFER_START_ADDRESS, core, (tmp + tile_offset) >> 5);
|
||||
utmp = read_emac(num_emac, EMAC_TX_CONTROL + EMAC_TX_BUFFER_START_ADDRESS, core);
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" TX Buffer set to @%x\n", tmp));
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" TX Buffer %p (%lx phys)\n", rckemacif->tx_buffer, virt_to_phys((uint32_t)rckemacif->tx_buffer)));
|
||||
write_emac(num_emac, EMAC_TX_CONTROL + EMAC_TX_BUFFER_START_ADDRESS, core, (uint32_t) (((uint64_t) virt_to_phys((uint32_t)rckemacif->tx_buffer) + tile_offset) >> 5));
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" TX Buffer set to @%x\n", read_emac(num_emac, EMAC_TX_CONTROL + EMAC_TX_BUFFER_START_ADDRESS, core)));
|
||||
|
||||
/* Get buffer read offset */
|
||||
read_offset = read_emac(num_emac, EMAC_TX_CONTROL + EMAC_TX_BUFFER_READ_OFFSET, core);
|
||||
/* Get buffer read offset */
|
||||
read_offset = read_emac(num_emac, EMAC_TX_CONTROL + EMAC_TX_BUFFER_READ_OFFSET, core);
|
||||
LWIP_DEBUGF(NETIF_DEBUG, (" TX Buffer read offset at: %d\n", read_offset));
|
||||
|
||||
/* Set buffer write offset to read offset */
|
||||
|
|
@ -717,7 +757,7 @@ err_t rckemacif_init(struct netif* netif)
|
|||
/* administrative details */
|
||||
netif->name[0] = 'e';
|
||||
netif->name[1] = 'n';
|
||||
netif->num = num;
|
||||
netif->num = 0;
|
||||
/* downward functions */
|
||||
netif->output = etharp_output;
|
||||
netif->linkoutput = rckemacif_output;
|
||||
|
|
|
|||
|
|
@ -31,10 +31,10 @@
|
|||
typedef struct rckemacif {
|
||||
struct eth_addr *ethaddr;
|
||||
/* Add whatever per-interface state that is needed here. */
|
||||
uint8_t* tx_buffer;
|
||||
uint8_t* rx_buffer;
|
||||
uint32_t rx_buffer_max;
|
||||
uint32_t rx_read_offset;
|
||||
uint8_t* tx_buffer;
|
||||
uint32_t tx_buffer_max;
|
||||
uint32_t tx_write_offset;
|
||||
void* irq_address;
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue