/* 
 * Copyright 2013 Steffen Vogel, Chair for Operating Systems,
 *                               RWTH Aachen University
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 * This file is part of MetalSVM. 
 */
 
 /**
 * @author Steffen Vogel
 * @file arch/x86/kernel/pmc.c
 * @brief Simple interface to IA32 Performance Monitor Counters
 *
 * This implementation is in parts specific for Intel Core 2 Duo Processors!
 * General purpose PMCS => pmc_gp_*()
 * Fixed function PMCs =>  pmc_ff_*()
 */

#include <errno.h>
#include <asm/pmc.h>
#include <asm/processor.h>

static struct pmc_caps caps = { 0 };

struct pmc_caps* pmc_init()
{
	if (!caps.version) {
		uint32_t a, b, c, d;
		cpuid(0x0A, &a, &b, &c, &d);

		caps.version     = (a >>  0) & 0xff;
		caps.gp_count    = (a >>  8) & 0xff;
		caps.gp_width    = (a >> 16) & 0xff;
		caps.ff_count    = (d >>  0) & 0x1f;
		caps.ff_width    = (d >>  5) & 0xff;
		caps.arch_events = (b >>  0) & 0x3f;

		// check if IA32_PERF_CAPABILITIES MSR is available
		if (caps.version >= 2) {
			cpuid(0x01, &a, &b, &c, &d);
			if (c & (1 << 15 /* PDCM */))
				caps.msr = rdmsr(IA32_PERF_CAPABILITIES);
		}
	}

	return &caps;
}

int pmc_gp_config(uint8_t i, uint16_t event, uint32_t flags, uint8_t umask, uint8_t cmask)
{
	if (BUILTIN_EXPECT(i > caps.gp_count, 0))
		return -EINVAL;

	uint64_t evtsel = flags | event;
	evtsel |= (cmask << PMC_EVTSEL_CMASK) | (umask << PMC_EVTSEL_UMASK);

	wrmsr(IA32_PERFEVTSEL(i), evtsel);
	wrmsr(IA32_PMC(i), 0); // reset counter

	return 0;
}

int pmc_ff_config(uint8_t i, uint8_t flags)
{
	if (BUILTIN_EXPECT(i > caps.ff_count, 0))
		return -EINVAL;


	uint64_t ctrl = rdmsr(MSR_PERF_FIXED_CTR_CTRL);

	ctrl &= ~(0x0f << i*4); // clear flags
	ctrl |= (flags & 0xf) << i*4;

	wrmsr(MSR_PERF_FIXED_CTR_CTRL, ctrl);

	return 0;
}

inline int pmc_gp_start(uint8_t i)
{
	if (BUILTIN_EXPECT(i > caps.gp_count, 0))
		return -EINVAL;

	wrmsr(IA32_PERFEVTSEL(i), rdmsr(IA32_PERFEVTSEL(i)) | PMC_EVTSEL_EN);

	return 0;
}

inline int pmc_gp_stop(uint8_t i)
{
	if (BUILTIN_EXPECT(i > caps.gp_count, 0))
		return -EINVAL;

	wrmsr(IA32_PERFEVTSEL(i), rdmsr(IA32_PERFEVTSEL(i)) & ~PMC_EVTSEL_EN);

	return 0;
}

inline int pmc_ff_start(uint8_t i)
{
	if (BUILTIN_EXPECT(i > caps.ff_count, 0))
		return -EINVAL;

	// TODO

	return 0;
}

inline int pmc_ff_stop(uint8_t i)
{
	if (BUILTIN_EXPECT(i > caps.ff_count, 0))
		return -EINVAL;

	// TODO

	return 0;
}

inline int pmc_start_all()
{
	if (BUILTIN_EXPECT(caps.version < 2, 0))
		return -EINVAL;

	wrmsr(MSR_PERF_GLOBAL_CTRL, -1L);

	return 0;
}

inline int pmc_stop_all()
{
	if (BUILTIN_EXPECT(caps.version < 2, 0))
		return -EINVAL;

	wrmsr(MSR_PERF_GLOBAL_CTRL, 0);

	return 0;
}

inline int pmc_reset_all()
{
	if (BUILTIN_EXPECT(caps.version < 2, 0))
		return -EINVAL;

	int i;
	for (i = 0; i < caps.gp_count; i++)
		pmc_gp_write(i, 0);

	for (i = 0; i < caps.ff_count; i++)
		pmc_ff_write(i, 0);

	return 0;
}

inline uint64_t pmc_gp_read(uint8_t i)
{
	if (BUILTIN_EXPECT(i > caps.gp_count, 0))
		return 0;

	return rdmsr(IA32_PMC(i));

	return 0;
}

inline uint64_t pmc_ff_read(uint8_t i)
{
	if (BUILTIN_EXPECT(i > caps.ff_count, 0))
		return 0;

	return rdmsr(MSR_PERF_FIXED_CTR(i));

	return 0;
}

inline int pmc_gp_write(uint8_t i, uint64_t val)
{
	if (BUILTIN_EXPECT(i > caps.gp_count, 0))
		return -EINVAL;

	if (caps.version >= 2 && caps.msr & (1 << 13 /* FW_WRITE */))
		wrmsr(IA32_A_PMC(i), val);
	else
		wrmsr(IA32_PMC(i), val);

	return 0;
}

inline int pmc_ff_write(uint8_t i, uint64_t val)
{
	if (BUILTIN_EXPECT(i > caps.ff_count, 0))
		return -EINVAL;

	wrmsr(MSR_PERF_FIXED_CTR(i), val);

	return 0;
}