/* * Copyright 2010 Stefan Lankes, Chair for Operating Systems, * RWTH Aachen University * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * This file is part of MetalSVM. */ #ifndef __ARCH_ATOMIC_H__ #define __ARCH_ATOMIC_H__ #include #ifdef __cplusplus extern "C" { #endif #if MAX_CORES > 1 #define LOCK "lock ; " #else #define LOCK "" #endif #define ATOMIC_INIT(i) { (i) } typedef struct { volatile int32_t counter; } atomic_int32_t; /* * Intel manuals: If a memory operand is referenced, the processor's locking * protocol is automatically implemented for the duration of the exchange * operation, regardless of the presence or absence of the LOCK prefix. */ inline static int32_t atomic_int32_test_and_set(atomic_int32_t* d, int32_t ret) { asm volatile ("xchgl %0, %1" : "=r"(ret) : "m"(d->counter), "0"(ret) : "memory"); return ret; } inline static int32_t atomic_int32_add(atomic_int32_t *d, int32_t i) { int32_t res = i; asm volatile(LOCK "xaddl %0, %1" : "=r"(i) : "m"(d->counter), "0"(i)); return res+i; } inline static int32_t atomic_int32_sub(atomic_int32_t *d, int32_t i) { return atomic_int32_add(d, -i); } inline static int32_t atomic_int32_inc(atomic_int32_t* d) { return atomic_int32_add(d, 1); } inline static int32_t atomic_uint32_dec(atomic_int32_t* d) { return atomic_int32_add(d, -1); } inline static int32_t atomic_int32_read(atomic_int32_t *d) { return d->counter; } inline static void atomic_int32_set(atomic_int32_t *d, int32_t v) { d->counter = v; } #ifdef __cplusplus } #endif #endif