/* 
 * Copyright 2010 Stefan Lankes, Chair for Operating Systems,
 *                               RWTH Aachen University
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 * This file is part of MetalSVM.
 */

#include <metalsvm/stdio.h>
#include <metalsvm/errno.h>
#include <metalsvm/processor.h>
#include <metalsvm/errno.h>
#include <asm/io.h>
#include <asm/RCCE_lib.h>
#include <asm/SCC_API.h>

#ifdef CONFIG_ROCKCREEK

#define CCR_INTR_ACTIVE		0x02

//scc_info_t	scc_info;
static char*	rcce_argv[] = {"MetalSVM", "1", "533", "0"};
static int 	rcce_argc = 4;

/*
 * This is a modified MPB program, which is part of the RCCE distribution (src/mpb.c).
 */
static int scc_reset(void)
{
	int tmp, x, y, z, offset;

	// Initialize API
	InitAPI(0);
  
	// Find out who I am...
	tmp=ReadConfigReg(CRB_OWN+MYTILEID); 
	x=(tmp>>3) & 0x0f; // bits 06:03
	y=(tmp>>7) & 0x0f; // bits 10:07
	z=(tmp   ) & 0x07; // bits 02:00

	// Allocate Message Passing Buffer
	t_vcharp MPB;
	MPBalloc(&MPB, x, y, z, 1); 
	if (!MPB) {
		kprintf("Unable to allocate MPB for core %d of Tile x=%d, y= %d! Exiting.\n", z, x, y);
		return 255;
	}

	// zap own MPB
	for (offset=0; offset < 0x2000; offset+=8)
		*(volatile unsigned long long int*)(MPB+offset) = 0;

	// Clear test&set register write. Next read-access will read "1" (lock granted).
	SetConfigReg(CRB_ADDR(x,y)+((z)?LOCK1:LOCK0), 1); 

	return 0;
}

int scc_init(void)
{
//	uint32_t x, y, z;
//	uint32_t tmp;
	int num_ranks;
	int my_rank;

	return 0;

	kprintf("Initialize Rock Creek!\n");
	if (RCCE_init(&rcce_argc, &rcce_argv) != RCCE_SUCCESS)
		return -ENODEV;

	my_rank   = RCCE_ue();
	num_ranks = RCCE_num_ues();
	kprintf("Got rank %d of %d ranks\n", my_rank, num_ranks);

	/* synchronize before starting MetalSVM: */
	RCCE_barrier(&RCCE_COMM_WORLD);

	/*tmp = *((uint32_t*) (CRB_OWN+MYTILEID));
	x=(tmp>>3) & 0x0f; // bits 06:03
	y=(tmp>>7) & 0x0f; // bits 10:07
	z=(tmp   ) & 0x07; // bits 02:00
	scc_info.pid = PID(x, y, z);
	kprintf("SCC Processor Id: %u (%u,%u,%u)\n", scc_info.pid, x, y, z);
*/
	/* default values for 16 GB system */
	/*scc_info.private_mem[0].low  = 0x00;
	scc_info.private_mem[0].high = 0x13FFFFFF; 
	scc_info.private_mem[1].low  = 0xFF000000;
	scc_info.private_mem[1].high = 0xFFFFFFFF;
*/
//	tmp = *((uint32_t*) (CRB_OWN+GCBCFG));
//	tmp = (tmp & 0x3FFFFFF) >> 7;
	//kprintf("Own GCBCFG is 0x%x\n", tmp);
/*	if (tmp == 0x70E1) {
		scc_info.tile_frequency = 800;
		scc_info.router_frequency = 1600;
	} else {
		scc_info.tile_frequency = 533;
		scc_info.router_frequency = 800;
	}
*/

/*	kprintf("The default tile frequency is %u MHz\nThe default router frequency is %u MHz\n",
		scc_info.tile_frequency, scc_info.router_frequency);

	if (z == 0)
		tmp = *((uint32_t*) (CRB_OWN+GLCFG0));
	else if (z == 1)
		tmp = *((uint32_t*) (CRB_OWN+GLCFG1));
	else
		tmp = 0;
*/
	/* set INTR to enable maskable interrupts */
/*	tmp = tmp | CCR_INTR_ACTIVE;
	if (z == 0)
		*((uint32_t*) (CRB_OWN+GLCFG0)) = tmp;
	else if (z == 1)
		*((uint32_t*) (CRB_OWN+GLCFG1)) = tmp;
*/
	/* reload core configuration */
/*	tmp = 0;
	if (z == 0)
		tmp = *((uint32_t*) (CRB_OWN+GLCFG0));
	else if (z == 1)
		tmp = *((uint32_t*) (CRB_OWN+GLCFG1));
	kprintf("Core Configuration %u: 0x%x\n", z, tmp);
*/

	kputs("Now, the SCC is initialized!\n");

	return 0;
}

#endif