335 lines
11 KiB
C
335 lines
11 KiB
C
//
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// Copyright 2010 Intel Corporation
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//
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// Project : bareMetal BIOS
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// File name : config.h
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// Author : mriepen
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// Date : 2008-06-24
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// Revision : 1.01
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//
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// Description : Header file for config.c
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//
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// Revision history:
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//
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// mri 1.01 2008-06-24
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// - Initial implementation
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//
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// ------------------------------------------------------------------------------------------------
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#ifndef __SCC_API_H__
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#define __SCC_API_H__
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// #########################################################################################
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// ____ _ _
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// / ___| _ _ _ __ ___ | |__ ___ | |___
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// \___ \| | | | '_ ` _ \| '_ \ / _ \| / __|
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// ___) | |_| | | | | | | |_) | (_) | \__
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// |____/ \__, |_| |_| |_|_.__/ \___/|_|___/
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// |___/
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//
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// #########################################################################################
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// Define start address of pagetable (PAGE_DIR_BASE should be equal to or above to STACK_TOP setting
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// in "../../bootcode/bootImage/defines.h" and needs to be 1025*4KB below the max private address)
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// and the number of available private slots... E.g.:
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// Private space for 2 cores on 1GB of memory (MCEMU single node): 0x00000000 to 0x29ffffffff (30 slots = 480MB)
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// Private space for 8 cores on 1GB of memory (MCEMU multi node): 0x00000000 to 0x05ffffffff ( 6 slots = 96MB)
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#define PRIV_SLOTS 6
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#define PAGE_DIR_BASE 0x04B00000
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// Symbols for MPB malloc
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#define MPBADDRBITS 13
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#define MPBSIZE (1<<MPBADDRBITS)
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#ifdef SHMADD
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// 64MB
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//#define SHMADDRBITS 26
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// 128MB
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//#define SHMADDRBITS 27
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// 256MB
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//#define SHMADDRBITS 28
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// 512MB
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#define SHMADDRBITS 29
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#define SHMSIZE (1<<SHMADDRBITS)
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// 960MB
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//#define SHMSIZE 0x3C000000
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#else
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#define SHMADDRBITS 26
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#define SHMSIZE (1<<SHMADDRBITS)
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#endif
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#define NUM_ROWS 4
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#define NUM_COLS 6
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#define NUM_CORES 2
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#define CRB_ADDR(x,y) (CRB_X0_Y0+(0x01000000*x)+(0x01000000*NUM_COLS*y))
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#define MPB_ADDR(x,y,z) (MPB_X0_Y0+(0x01000000*x)+(0x01000000*NUM_COLS*y)+(MPBSIZE*z))
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#define TID(x,y) ((y<<4)+x)
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#define X_TID(tid) (tid&0x0f)
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#define Y_TID(tid) (tid>>4)
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#define PID(x,y,core) ((NUM_CORES*NUM_COLS*y)+(NUM_CORES*x)+core)
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#define X_PID(pid) ((pid/NUM_CORES)-(NUM_COLS*Y_PID(pid)))
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#define Y_PID(pid) ((pid/NUM_CORES)/NUM_COLS)
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#define Z_PID(pid) (pid%NUM_CORES)
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// Symbols for shared memory
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#ifdef SHMADD
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#define SHM_X0_Y0 0x84000000
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#define SHM_X5_Y0 0x85000000
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#define SHM_X0_Y2 0x86000000
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#define SHM_X5_Y2 0x87000000
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#else
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#define SHM_X0_Y0 0x80000000
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#define SHM_X5_Y0 0x81000000
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#define SHM_X0_Y2 0x82000000
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#define SHM_X5_Y2 0x83000000
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#endif
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#define SHM_ADDR SHM_X0_Y0
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// Symbols for MPB addresses
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#define MPB_X0_Y0 0xc0000000
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#define MPB_X1_Y0 0xc1000000
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#define MPB_X2_Y0 0xc2000000
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#define MPB_X3_Y0 0xc3000000
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#define MPB_X4_Y0 0xc4000000
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#define MPB_X5_Y0 0xc5000000
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#define MPB_X0_Y1 0xc6000000
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#define MPB_X1_Y1 0xc7000000
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#define MPB_X2_Y1 0xc8000000
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#define MPB_X3_Y1 0xc9000000
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#define MPB_X4_Y1 0xca000000
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#define MPB_X5_Y1 0xcb000000
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#define MPB_X0_Y2 0xcc000000
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#define MPB_X1_Y2 0xcd000000
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#define MPB_X2_Y2 0xce000000
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#define MPB_X3_Y2 0xcf000000
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#define MPB_X4_Y2 0xd0000000
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#define MPB_X5_Y2 0xd1000000
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#define MPB_X0_Y3 0xd2000000
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#define MPB_X1_Y3 0xd3000000
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#define MPB_X2_Y3 0xd4000000
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#define MPB_X3_Y3 0xd5000000
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#define MPB_X4_Y3 0xd6000000
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#define MPB_X5_Y3 0xd7000000
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#define MPB_OWN 0xd8000000
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// Symbols for CRB addresses
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#define CRB_X0_Y0 0xe0000000
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#define CRB_X1_Y0 0xe1000000
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#define CRB_X2_Y0 0xe2000000
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#define CRB_X3_Y0 0xe3000000
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#define CRB_X4_Y0 0xe4000000
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#define CRB_X5_Y0 0xe5000000
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#define CRB_X0_Y1 0xe6000000
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#define CRB_X1_Y1 0xe7000000
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#define CRB_X2_Y1 0xe8000000
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#define CRB_X3_Y1 0xe9000000
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#define CRB_X4_Y1 0xea000000
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#define CRB_X5_Y1 0xeb000000
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#define CRB_X0_Y2 0xec000000
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#define CRB_X1_Y2 0xed000000
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#define CRB_X2_Y2 0xee000000
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#define CRB_X3_Y2 0xef000000
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#define CRB_X4_Y2 0xf0000000
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#define CRB_X5_Y2 0xf1000000
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#define CRB_X0_Y3 0xf2000000
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#define CRB_X1_Y3 0xf3000000
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#define CRB_X2_Y3 0xf4000000
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#define CRB_X3_Y3 0xf5000000
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#define CRB_X4_Y3 0xf6000000
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#define CRB_X5_Y3 0xf7000000
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#define CRB_OWN 0xf8000000
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// FPGA registers
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#define FPGA_BASE 0xf9000000
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// Symbol for RPC
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#define RPC_BASE 0xfb000000
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// Symbols for CRB sub-addresses
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#define GLCFG0 0x010
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#define GLCFG1 0x018
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#define L2CFG0 0x020
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#define L2CFG1 0x028
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#define SENSOR 0x040
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#define GCBCFG 0x080
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#define MYTILEID 0x100
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#define LOCK0 0x200
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#define LOCK1 0x400
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#define LUT0 0x00800
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#define LUT1 0x01000
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// Symbols for GLSTATn bit positions and ranges
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// of status values (Read only)
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#define GLSTAT_RANGE 26:13
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#define GLSTAT_XBP3_BIT 26
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#define GLSTAT_XBP2_BIT 25
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#define GLSTAT_XPM1_BIT 24
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#define GLSTAT_XPM0_BIT 23
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#define GLSTAT_XIERRNN_BIT 22
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#define GLSTAT_XFERRNN_BIT 21
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#define GLSTAT_XPRDY_BIT 20
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#define GLSTAT_XSMIACTNN_BIT 19
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#define GLSTAT_SHDWN_BIT 18
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#define GLSTAT_FLUACK_BIT 17
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#define GLSTAT_HALT_BIT 16
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#define GLSTAT_WRBACK_BIT 15
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#define GLSTAT_FLUSH_BIT 14
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#define GLSTAT_BRTRMSG_BIT 13
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// Symbols for GLCFGn bit positions and ranges
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// of configuration and IRQ values (Read-Write)
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#define GLCFG_RANGE 12:00
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#define GLCFG_XPICD_RANGE 12:11
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#define GLCFG_CPUTYP_BIT 10
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#define GLCFG_XA20MNN_BIT 09
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#define GLCFG_XSMINN _BIT 08
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#define GLCFG_XSTPCLKNN_BIT 06
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#define GLCFG_XRSNN_BIT 05
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#define GLCFG_XIGNNENN_BIT 04
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#define GLCFG_XFLSHNN_BIT 03
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#define GLCFG_XINIT_BIT 02
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#define GLCFG_XINTR_BIT 01
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#define GLCFG_XNMI_BIT 00
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// Sybols for L2CFGn bit positions and ranges
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#define L2CFG_RANGE 13:00
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#define L2CFG_STOPL2CCCLK_BIT 13
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#define L2CFG_STOPL2ARRAYCLK_BIT 12
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#define L2CFG_BLFLOATEN_BIT 11
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#define L2CFG_WLSLPEN_BIT 10
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#define L2CFG_WTSLPEN_BIT 09
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#define L2CFG_FLIPEN_BIT 08
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#define L2CFG_DATAECCEN_BIT 07
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#define L2CFG_TAGECCEN_BIT 06
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#define L2CFG_SLPBYPASS_BIT 05
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#define L2CFG_WAYDISABLE_BIT 04
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#define L2CFG_BBL2SLPPGM_RANGE 03:00
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// Sybols for SENSOR bit positions and ranges
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#define SENSOR_EN_BIT 13
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#define SENSOR_GATE_PULSE_CNT_RANGE 12:00
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// Sybols for GCBCFG bit positions and ranges
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#define GCBCFG_RXB_CLKRATIO_RANGE 25:19
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#define GCBCFG_TILE_CLKRATIO_RANGE 18:12
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#define GCBCFG_TILE_CLKDIV_RANGE 11:08
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#define GCBCFG_L2_1_SYNCRESETEN_BIT 07
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#define GCBCFG_L2_0_SYNCRESETEN_BIT 06
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#define GCBCFG_CORE1_SYNCRESETEN_BIT 05
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#define GCBCFG_CORE0_SYNCRESETEN_BIT 04
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#define GCBCFG_L2_1_RESET_BIT 03
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#define GCBCFG_L2_0_RESET_BIT 02
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#define GCBCFG_CORE1_RESET_BIT 01
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#define GCBCFG_CORE0_RESET_BIT 00
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// Tile-ID (Read Only bits)
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#define TID_XPOS_RANGE 10:07
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#define TID_YPOS_RANGE 06:03
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#define TID_SYS2MIFDESTID 02:00
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// Lock registers
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#define LOCK_BIT 00
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// MPB pointer type
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//typedef volatile unsigned char* t_vcharp;
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// #########################################################################################
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// _____ _ _
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// | ___| _ _ __ ___| |_(_) ___ _ __ ___
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// | |_ | | | | '_ \ / __| __| |/ _ \| '_ \/ __|
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// | _|| |_| | | | | (__| |_| | (_) | | | \__
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// |_| \__,_|_| |_|\___|\__|_|\___/|_| |_|___/
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//
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// #########################################################################################
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// InitAPI opens the RCKMEM device drivers. This routine needs to be invoked
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// once before using any other API functions! The successmessage can be disabled.
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//
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// Parameter: printMessages (0: No messages / 1: Messages enabled)
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// Return value: %
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//
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void InitAPI(int printMessages);
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// SetConfigBit writes a bit to a specified config register using read-modify-write. Only use
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// function to access memory locations that are not (!) performance critical (e.g. Tile-ID).
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// Use MallocConfigReg() function for performance critical memory locations!
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//
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// Parameter: ConfigAddr - Address of configuration register...
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// BitPos - Bit position within config register to set/reset
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// BitValue - Value to write to specified bit...
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//
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void SetConfigBit(unsigned int ConfigAddr, int BitPos, int BitValue);
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// SetConfigReg writes a value to a specified config register using a single write. Only use
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// function to access memory locations that are not (!) performance critical (e.g. Tile-ID).
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// Use MallocConfigReg() function for performance critical memory locations!
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//
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// Parameter: ConfigAddr - Address of configuration register...
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// RegValue - Value to write to specified register...
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//
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void SetConfigReg(unsigned int ConfigAddr, int RegValue);
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// ReadConfigReg reads a value from a specified config register using a single read. Only use
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// function to access memory locations that are not (!) performance critical (e.g. Tile-ID).
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// Use MallocConfigReg() function for performance critical memory locations!
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//
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// Parameter: ConfigAddr - Address of configuration register...
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// BitPos - Bit position within config register to set/reset
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// BitValue - Value to write to specified bit...
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//
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int ReadConfigReg(unsigned int ConfigAddr);
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// MallocConfigReg performs a memory map operation on ConfigAddr (physical address) and
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// returns a virtual address that can be used in the application. Use this function to
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// allocate memory locations that you access frequently!
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//
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// Parameter: ConfigAddr - Physical address of configuration register.
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//
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// Return value: ConfigRegVirtualAddr - Virtual address of configuration register.
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//
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int* MallocConfigReg(unsigned int ConfigAddr);
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// FreeConfigReg unmaps a memory location that has been mapped with the MallocConfigReg()
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// function...
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//
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// Parameter: ConfigRegVirtualAddr - Virtual address of configuration register.
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//
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void FreeConfigReg(int* ConfigRegVirtualAddr);
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// MPBalloc allocates MPBSIZE bytes of MessagePassing buffer Memory at MPB_ADDR(x,y,core).
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//
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// Parameter: MPB - Pointer to MPB area (return value, virtal address)
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// x,y,core - Position of tile (x,y) and core...
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//
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//#ifdef SCC
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void MPBalloc(t_vcharp *MPB, int x, int y, int core, int isOwnMPB);
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void SHMalloc(t_vcharp *SHM);
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//#endif
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// MPBunalloc unallocates an allocated MPB area.
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//
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// Parameter: MPB - Pointer to MPB area (virtual address)
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//
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void MPBunalloc(t_vcharp *MPB);
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void SHMunalloc(t_vcharp *SHM);
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#ifdef SHMADD_CACHEABLE
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int DCMflush();
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#endif
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#endif
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