233 lines
12 KiB
C
233 lines
12 KiB
C
/*
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* Copyright 2010 Stefan Lankes, Chair for Operating Systems,
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* RWTH Aachen University
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* This file is part of MetalSVM.
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*
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* This code based mostly on the online manual http://www.lowlevel.eu/wiki/RTL8139
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*/
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#ifndef __HAVE_RTL8139_H__
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#define __HAVE_RTL8139_H__
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#include <metalsvm/stddef.h>
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#include <metalsvm/spinlock.h>
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#if defined(CONFIG_LWIP) && defined(CONFIG_PCI)
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// the registers are at the following places
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#define IDR0 0x0 // the ethernet ID (6bytes)
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#define MAR0 0x8 // Multicast (8 bytes)
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#define TSD0 0x10 // transmit status of each descriptor (4bytes/descriptor) (C mode)
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#define DTCCR 0x10 // Dump Tally Counter Command Register (C+ mode)
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#define TSAD0 0x20 // transmit start address of descriptor 0 (4byte, C mode, 4 byte alignment)
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#define TSAD1 0x24 // transmit start address of descriptor 1 (4byte, C mode, 4 byte alignment)
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#define TNPDS 0x20 // transmit normal priority descriptors start address (8bytes, C+ mode, 256 byte-align)
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#define TSAD2 0x28 // transmit start address of descriptor 2 (4byte, C mode, 4 byte alignment)
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#define TSAD3 0x2c // transmit start address of descriptor 3 (4byte, C mode, 4 byte alignment)
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#define THPDS 0x28 // transmit high priority descriptors start address (8byte, C+ mode, 256 byte-align)
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#define RBSTART 0x30 // recieve buffer start address (C mode, 4 byte alignment)
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#define ERBCR 0x34 // early recieve byte count (2byte)
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#define ERSR 0x36 // early recieve state register (1byte)
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#define CR 0x37 // command register (1byte)
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#define CAPR 0x38 // current address of packet read (2byte, C mode, initial value 0xFFF0)
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#define CBR 0x3a // current buffer address , total recieved byte-count in the Rx buffer (2byte, C mode, initial value 0x0000)
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#define IMR 0x3c // interrupt mask register (2byte)
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#define ISR 0x3e // interrupt status register (2byte)
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#define TCR 0x40 // transmit config register (4byte)
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#define RCR 0x44 // receive config register (4byte)
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#define TCTR 0x48 // timer count register, write any value and it will reset the count, and count from zero (4byte)
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#define MPC 0x4C // missed packet count , number of packets ignored due to RX overflow, 24-bit, write a value to reset (4byte, top is void)
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#define CR9346 0x50 // command register for 93C46 (93C56) (1byte)
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#define CONFIG0 0x51 // config register 0 (1byte)
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#define CONFIG1 0x52 // config register 1 (1byte)
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#define TIMINT 0x54 // timer interrupt register , the timeout bit will be set when the value of this == value of TCTR (4byte, when 0 does nothing)
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#define MSR 0x58 // media status register (1byte)
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#define CONFIG3 0x59 // config register 3 (1byte)
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#define CONFIG4 0x5a // config register 4 (1byte)
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#define MULINT 0x5c // multiple interrupt select (4byte)
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#define RERID 0x5e // revision ID (C+ = 0x10)
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#define TSAD 0x60 // transmit status of ALL descriptors (2byte, C mode)
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#define BMCR 0x62 // basic mode control register (2byte)
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#define BMSR 0x64 // basic mode status register (2byte)
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#define ANAR 0x66 // Auto-negotiation advertisement register (2byte)
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#define ANLPAR 0x68 // Auto-negotiation link partner register (2byte)
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#define ANER 0x6a // Auto-negotiation expansion register (2byte)
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#define DIS 0x6c // disconnected counter (2byte)
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#define FCSC 0x6e // false carrier sense counter (2byte)
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#define NWAYTR 0x70 // N-way test register (2byte)
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#define REC 0x72 // RX_ER (counts valid packets) counter (2byte)
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#define CSCR 0x74 // CS config register (2byte)
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#define PHYS1P 0x78 // PHY parameter 1 (2byte)
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#define TWP 0x7c // twister parameter (2byte)
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#define PHYS2P 0x80 // PHY parameter 2
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// some power managment registers are here
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#define FLASH 0xD4 // flash memory read/write (4byte)
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#define CONFIG5 0xD8 // config register 5 (1byte)
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#define TPPoll 0xD9 // transmit priority polling (1byte, C+ mode)
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#define CPCR 0xE0 // C+ command register (2byte, C+ mode)
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#define RDSAR 0xE4 // C+ receive descriptor start address (4byte, C+ mode, 256 byte alignment)
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#define ETTR 0xEC // C+ early transmit threshold (1byte, C+ mode)
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// some cardbus only stuff goes here
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#define MIIR 0xFC // MII register (Auto-detect or MII mode only)
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// Command Register
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#define CR_RST 0x10 // Reset, set to 1 to invoke S/W reset, held to 1 while resetting
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#define CR_RE 0x08 // Reciever Enable, enables receiving
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#define CR_TE 0x04 // Transmitter Enable, enables transmitting
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#define CR_BUFE 0x01 // Rx buffer is empty
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// Transmit Configuration Register
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#define TCR_HWVERID 0x7CC00000 // mask for hw version ID's
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#define TCR_HWOFFSET 22
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#define TCR_IFG 0x3000000 // interframe gap time
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#define TCR_LBK1 0x40000 // loopback test
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#define TCR_LBK0 0x20000 // loopback test
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#define TCR_CRC 0x10000 // append CRC (card adds CRC if 1)
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#define TCR_MXDMA2 0x400 // max dma burst
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#define TCR_MXDMA1 0x200 // max dma burst
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#define TCR_MXDMA0 0x100 // max dma burst
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#define TCR_TXRR 0xF0 // Tx retry count, 0 = 16 else retries TXRR * 16 + 16 times
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#define TCR_CLRABT 0x01 // Clear abort, attempt retransmit (when in abort state)
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// Media Status Register
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#define MSR_TXFCE 0x80 // Tx Flow Control enabled
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#define MSR_RXFCE 0x40 // Rx Flow Control enabled
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#define MSR_AS 0x10 // Auxilary status
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#define MSR_SPEED 0x8 // set if currently talking on 10mbps network, clear if 100mbps
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#define MSR_LINKB 0x4 // Link Bad ?
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#define MSR_TXPF 0x2 // Transmit Pause flag
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#define MSR_RXPF 0x1 // Recieve Pause flag
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// Basic mode control register
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#define BMCR_RESET 0x8000 // set the status and control of PHY to default
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#define BMCR_SPD100 (1 << 13) // 100 MBit
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#define BMCR_SPD1000 (1 << 6) // 1000 MBit
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#define BMCR_ANE 0x1000 // enable N-way autonegotiation (ignore above if set)
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#define BMCR_RAN 0x400 // restart auto-negotiation
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#define BMCR_DUPLEX 0x200 // Duplex mode, generally a value of 1 means full-duplex
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// Receive Configuration Register
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#define RCR_ERTH3 0x8000000 // early Rx Threshold 0
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#define RCR_ERTH2 0x4000000 // early Rx Threshold 1
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#define RCR_ERTH1 0x2000000 // early Rx Threshold 2
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#define RCR_ERTH0 0x1000000 // early Rx Threshold 3
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#define RCR_MRINT 0x20000 // Multiple Early interrupt, (enable to make interrupts happen early, yuk)
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#define RCR_RER8 0x10000 // Receive Error Packets larger than 8 bytes
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#define RCR_RXFTH2 0x8000 // Rx Fifo threshold 0
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#define RCR_RXFTH1 0x4000 // Rx Fifo threshold 1 (set to 110 and it will send to system when 1024bytes have been gathered)
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#define RCR_RXFTH0 0x2000 // Rx Fifo threshold 2 (set all these to 1, and it wont FIFO till the full packet is ready)
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#define RCR_RBLEN1 0x1000 // Rx Buffer length 0
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#define RCR_RBLEN0 0x800 // Rx Buffer length 1 (C mode, 11 = 64kb, 10 = 32k, 01 = 16k, 00 = 8k)
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#define RCR_MXDMA2 0x400 // Max DMA burst size 0
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#define RCR_MXDMA1 0x200 // Max DMA burst size 1
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#define RCR_MXDMA0 0x100 // Max DMA burst size 2
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#define RCR_WRAP 0x80 // (void if buffer size = 64k, C mode, wrap to beginning of Rx buffer if we hit the end)
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#define RCR_EEPROMSEL 0x40 // EEPROM type (0 = 9346, 1 = 9356)
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#define RCR_AER 0x20 // Accept Error Packets (do we accept bad packets ?)
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#define RCR_AR 0x10 // Accept runt packets (accept packets that are too small ?)
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#define RCR_AB 0x08 // Accept Broadcast packets (accept broadcasts ?)
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#define RCR_AM 0x04 // Accept multicast ?
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#define RCR_APM 0x02 // Accept Physical matches (accept packets sent to our mac ?)
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#define RCR_AAP 0x01 // Accept packets with a physical address ?
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// Interrupt Status/Mask Register
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// Bits in IMR enable/disable interrupts for specific events
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// Bits in ISR indicate the status of the card
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#define ISR_SERR 0x8000 // System error interrupt
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#define ISR_TUN 0x4000 // time out interrupt
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#define ISR_SWInt 0x100 // Software interrupt
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#define ISR_TDU 0x80 // Tx Descriptor unavailable
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#define ISR_FIFOOVW 0x40 // Rx Fifo overflow
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#define ISR_PUN 0x20 // Packet underrun/link change
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#define ISR_RXOVW 0x10 // Rx overflow/Rx Descriptor unavailable
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#define ISR_TER 0x08 // Tx Error
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#define ISR_TOK 0x04 // Tx OK
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#define ISR_RER 0x02 // Rx Error
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#define ISR_ROK 0x01 // Rx OK
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#define R39_INTERRUPT_MASK 0x7f
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// CR9346 Command register
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#define CR9346_EEM1 0x80 // determine the operating mode
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#define CR9346_EEM0 0x40 // 00 = Normal, 01 = Auto-load, 10 = Programming, 11 = Config, Register write enabled
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#define CR9346_EECS 0x8 // status of EECS
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#define CR9346_EESK 0x4 // status of EESK
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#define CR9346_EEDI 0x2 // status of EEDI
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#define CR9346_EEDO 0x1 // status of EEDO
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// CONFIG1 stuff
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#define CONFIG1_LEDS 0xC0 // leds status
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#define CONFIG1_DVRLOAD 0x20 // is the driver loaded ?
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#define CONFIG1_LWACT 0x10 // lanwake mode
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#define CONFIG1_MEMMAP 0x8 // Memory mapping enabled ?
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#define CONFIG1_IOMAP 0x4 // IO map enabled ?
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#define CONFIG1_VPD 0x2 // enable the virtal product data
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#define CONFIG1_PMEn 0x1 // Power Managment Enable
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// CONFIG3 stuff
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#define CONFIG3_GNT 0x80 // Grant Select enable
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#define CONFIG3_PARM 0x40 // Parameter auto-load enabled ?
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#define CONFIG3_MAGIC 0x20 // Magic packet ?
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#define CONFIG3_LINKUP 0x10 // wake computer when link goes up ?
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#define CONFIG3_CardB 0x08 // Card Bus stuff enabled ?
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#define CONFIG3_CLKRUN 0x04 // enable CLKRUN ?
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#define CONFIG3_FRE 0x02 // Function registers enabled ? (cardbus only)
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#define CONFIG3_FBBE 0x01 // fast back to back enabled ?
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// CONFIG4 stuff ?
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#define CONFIG4_RXFAC 0x80 // Clear Rx Fifo overflow, when enabled the card will clear FIFO overflow automatically
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#define CONFIG4_AnaOff 0x40 // Analogue power off ?
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#define CONFIG4_LWF 0x20 // Long wake-up frame
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#define CONFIG4_LWPME 0x10 // LANWAKE vs PMEB
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#define CONFIG4_LWPTN 0x04 // Lan wake pattern ?
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#define CONFIG4_PBWAKE 0x01 // pre-boot wakeup
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//Transmit Status of Descriptor0-3 (C mode only)
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#define TSD_CRS (1 << 31) // carrier sense lost (during packet transmission)
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#define TSD_TABT (1 << 30) // transmission abort
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#define TSD_OWC (1 << 29) // out of window collision
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#define TSD_CDH (1 << 28) // CD Heart beat (Cleared in 100Mb mode)
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#define TSD_NCC 0xF000000 // Number of collisions counted (during transmission)
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#define TSD_EARTH 0x3F0000 // threshold to begin transmission (0 = 8bytes, 1->2^6 = * 32bytes)
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#define TSD_TOK (1 << 15) // Transmission OK, successful
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#define TSD_TUN (1 << 14) // Transmission FIFO underrun
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#define TSD_OWN (1 << 13) // Tx DMA operation finished (driver must set to 0 when TBC is written)
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#define TSD_SIZE 0x1fff // Descriptor size, the total size in bytes of data to send (max 1792)
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/*
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* Helper struct to hold private data used to operate your ethernet interface.
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*/
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typedef struct rtl1839if {
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struct eth_addr *ethaddr;
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/* Add whatever per-interface state that is needed here. */
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uint8_t* tx_buffer[4];
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uint8_t* rx_buffer;
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uint32_t iobase;
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uint32_t tx_queue;
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uint32_t tx_complete;
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uint16_t rx_pos;
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uint8_t tx_inuse[4];
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uint8_t irq;
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volatile uint8_t polling;
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} rtl1839if_t;
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/*
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* Initialize the network driver for the RealTek RTL8139 family
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*/
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err_t rtl8139if_init(struct netif* netif);
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#endif
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#endif
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