1162 lines
27 KiB
NASM
1162 lines
27 KiB
NASM
;
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; Copyright 2010 Stefan Lankes, Chair for Operating Systems,
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; RWTH Aachen University
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;
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; Licensed under the Apache License, Version 2.0 (the "License");
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; you may not use this file except in compliance with the License.
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; You may obtain a copy of the License at
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;
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; http://www.apache.org/licenses/LICENSE-2.0
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;
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; Unless required by applicable law or agreed to in writing, software
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; distributed under the License is distributed on an "AS IS" BASIS,
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; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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; See the License for the specific language governing permissions and
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; limitations under the License.
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;
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; This file is part of MetalSVM.
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; This is the kernel's entry point. We could either call main here,
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; or we can use this to setup the stack or other nice stuff, like
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; perhaps setting up the GDT and segments. Please note that interrupts
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; are disabled at this point: More on interrupts later!
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%include "config.inc"
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[BITS 32]
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extern kernel_start ; defined in linker script
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extern kernel_end
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extern apic_mp
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; We use a special name to map this section at the begin of our kernel
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; => Multiboot needs its magic number at the beginning of the kernel
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SECTION .mboot
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global start
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start:
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jmp stublet
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; This part MUST be 4byte aligned, so we solve that issue using 'ALIGN 4'
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ALIGN 4
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mboot:
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; Multiboot macros to make a few lines more readable later
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MULTIBOOT_PAGE_ALIGN equ 1<<0
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MULTIBOOT_MEMORY_INFO equ 1<<1
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; MULTIBOOT_AOUT_KLUDGE equ 1<<16
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MULTIBOOT_HEADER_MAGIC equ 0x1BADB002
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MULTIBOOT_HEADER_FLAGS equ MULTIBOOT_PAGE_ALIGN | MULTIBOOT_MEMORY_INFO ; | MULTIBOOT_AOUT_KLUDGE
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MULTIBOOT_CHECKSUM equ -(MULTIBOOT_HEADER_MAGIC + MULTIBOOT_HEADER_FLAGS)
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EXTERN code, bss, end
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; This is the GRUB Multiboot header. A boot signature
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dd MULTIBOOT_HEADER_MAGIC
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dd MULTIBOOT_HEADER_FLAGS
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dd MULTIBOOT_CHECKSUM
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ALIGN 4
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; we need already a valid GDT to switch in the 64bit mode
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GDT64: ; Global Descriptor Table (64-bit).
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.Null: equ $ - GDT64 ; The null descriptor.
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dw 0 ; Limit (low).
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dw 0 ; Base (low).
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db 0 ; Base (middle)
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db 0 ; Access.
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db 0 ; Granularity.
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db 0 ; Base (high).
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.Code: equ $ - GDT64 ; The code descriptor.
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dw 0 ; Limit (low).
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dw 0 ; Base (low).
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db 0 ; Base (middle)
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db 10011000b ; Access.
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db 00100000b ; Granularity.
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db 0 ; Base (high).
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.Data: equ $ - GDT64 ; The data descriptor.
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dw 0 ; Limit (low).
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dw 0 ; Base (low).
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db 0 ; Base (middle)
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db 10010010b ; Access.
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db 00000000b ; Granularity.
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db 0 ; Base (high).
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.Pointer: ; The GDT-pointer.
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dw $ - GDT64 - 1 ; Limit.
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dq GDT64 ; Base.
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times 256 DD 0 ; stack for booting
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startup_stack:
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SECTION .data
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; create default page tables for the 64bit kernel
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global boot_pml4
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ALIGN 4096 ; of course, the page tables have to be page aligned
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MAP_ENTRIES equ 512
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boot_pml4 times 512 DQ 0
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boot_pdpt times 512 DQ 0
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boot_pd times 512 DQ 0
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boot_pt times (MAP_ENTRIES*512) DQ 0
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SECTION .text
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ALIGN 8
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%if MAX_CORES > 1
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global smp_entry
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smp_entry:
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; initialize cpu features
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call cpu_init
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; initialize cr3 register
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mov edi, boot_pml4
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mov cr3, edi
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; enable PAE
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mov eax, cr4
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or eax, 1 << 5
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mov cr4, eax
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; enable longmode (compatibility mode)
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mov ecx, 0xC0000080
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rdmsr
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or eax, 1 << 8
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wrmsr
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; enable paging
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mov eax, cr0
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or eax, 1 << 31 | 1 << 0 ; Set the PG-bit, which is the 31nd bit, and the PE-bit, which is the 0th bit.
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mov cr0, eax ; According to the multiboot spec the PE-bit has to be set by bootloader already!
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; jump to 64-bit longmode
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mov edi, [esp+4] ; set argumet for smp_start
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lgdt [GDT64.Pointer] ; Load the 64-bit global descriptor table.
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jmp GDT64.Code:smp_start64 ; Set the code segment and enter 64-bit long mode.
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jmp $ ; endless loop
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%endif
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; search MP Floating Pointer Structure
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search_mps:
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push ebp
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mov ebp, esp
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push ecx
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xor eax, eax
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mov ecx, [ebp+8]
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.l1:
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cmp [ecx], DWORD 0x5f504d5f ; MP_FLT_SIGNATURE
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jne .l2
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mov al, BYTE [ecx+9]
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cmp eax, 4
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ja .l2
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mov al, BYTE [ecx+11]
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cmp eax, 0
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jne .l2
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mov eax, ecx
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jmp .l3
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.l2:
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add ecx, 4
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cmp ecx, [ebp+12]
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jb .l1
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xor eax, eax
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.l3:
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pop ecx
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pop ebp
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ret
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check_longmode:
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; check for cpuid instruction
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pushfd
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pop eax
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mov ecx, eax
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xor eax, 1 << 21
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push eax
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popfd
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pushfd
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pop eax
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push ecx
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popfd
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xor eax, ecx
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jz .unsupported
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; check for extended cpu features (cpuid > 0x80000000)
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mov eax, 0x80000000
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cpuid
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cmp eax, 0x80000001
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jb .unsupported ; It is less, there is no long mode.
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; check if longmode is supported
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mov eax, 0x80000001
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cpuid
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test edx, 1 << 29 ; Test if the LM-bit, which is bit 29, is set in the D-register.
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jz .unsupported ; They aren't, there is no long mode.
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ret
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.unsupported:
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jmp $
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check_lapic:
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push eax
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push ebx
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push ecx
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push edx
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mov eax, 1
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cpuid
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and edx, 0x200
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cmp edx, 0
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je .unsupported
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; map lapic at 0xFEE00000 below the kernel
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mov edi, kernel_start - 0x1000
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shr edi, 9 ; (edi >> 12) * 8
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add edi, boot_pt
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mov ebx, 0xFEE00000 ; LAPIC base address
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or ebx, 0x00000013
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mov DWORD [edi], ebx
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.unsupported:
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pop edx
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pop ecx
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pop ebx
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pop eax
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ret
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cpu_init:
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mov eax, cr0
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; enable caching, disable paging and fpu emulation
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and eax, 0x1ffffffb
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; ...and turn on FPU exceptions
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or eax, 0x22
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mov cr0, eax
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; clears the current pgd entry
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xor eax, eax
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mov cr3, eax
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; at this stage, we disable the SSE support
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mov eax, cr4
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and eax, 0xfffbf9ff
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mov cr4, eax
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ret
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ALIGN 4
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stublet:
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mov esp, startup_stack-4
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; save pointer to the multiboot structure
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push ebx
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; initialize cpu features
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call cpu_init
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; check if longmode is supported
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call check_longmode
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; check if lapic is available
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call check_lapic
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; find MP Floating Pointer Structure
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push DWORD 0x100000
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push DWORD 0xF0000
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call search_mps
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add esp, 8
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cmp eax, 0
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jne map_mps
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push DWORD 0xA0000
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push DWORD 0x9F000
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call search_mps
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add esp, 8
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cmp eax, 0
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je map_kernel
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map_mps:
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; map MP Floating Pointer Structure
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mov DWORD [apic_mp], eax
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mov edi, eax
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and edi, 0xFFFFF000
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shr edi, 9 ; (edi >> 12) * 8
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add edi, boot_pt
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mov ebx, eax
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and ebx, 0xFFFFF000
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or ebx, 0x00000013
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mov DWORD [edi], ebx
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; map mp_config
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mov edi, [eax+4]
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and edi, 0xFFFFF000
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shr edi, 9 ; (edi >> 12) * 8
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add edi, boot_pt
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mov ebx, [eax+4]
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and ebx, 0xFFFFF000
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or ebx, 0x00000013
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mov DWORD [edi], ebx
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%ifdef CONFIG_VGA
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map_vga:
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mov edi, 0xB8000
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shr edi, 9 ; (edi >> 12) * 8
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add edi, boot_pt
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mov ebx, 0xB8000
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or ebx, 0x00000013
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mov DWORD [edi], ebx
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%endif
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map_multiboot:
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mov edi, [esp]
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and edi, 0xFFFFF000
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shr edi, 9 ; (edi >> 12) * 8
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add edi, boot_pt
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mov ebx, [esp]
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and ebx, 0xFFFFF000
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or ebx, 0x00000003
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mov DWORD [edi], ebx
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map_kernel:
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mov edi, kernel_start
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shr edi, 9 ; (kernel_start >> 12) * 8
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add edi, boot_pt
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mov ebx, kernel_start
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or ebx, 0x00000003
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mov ecx, kernel_end ; determine kernel size in number of pages
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sub ecx, kernel_start
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shr ecx, 12
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inc ecx
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.l1:
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mov DWORD [edi], ebx ; Set the double word at the destination index to the B-register.
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add edi, 8
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add ebx, 0x1000
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loop .l1
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init_paging:
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mov edi, boot_pml4
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mov cr3, edi
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; So lets make PML4T[0] point to the PDPT and so on:
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mov DWORD [edi], boot_pdpt ; Set the double word at the destination index to pdpt.
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or DWORD [edi], 0x00000003 ; Set present and writeable bit
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mov edi, boot_pdpt
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mov DWORD [edi], boot_pd ; Set the double word at the destination index to pd.
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or DWORD [edi], 0x00000003 ; Set present and writeable bit
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mov edi, boot_pd
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mov ebx, boot_pt
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mov ecx, MAP_ENTRIES
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.l1:
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mov DWORD [edi], ebx ; Set the double word at the destination index to pt.
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or DWORD [edi], 0x00000003 ; Set present and writeable bit
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add edi, 8
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add ebx, 0x1000
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loop .l1
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; enable PAE
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mov eax, cr4
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or eax, 1 << 5
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mov cr4, eax
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; enable longmode (compatibility mode)
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mov ecx, 0xC0000080
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rdmsr
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or eax, 1 << 8
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wrmsr
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; enable paging
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mov eax, cr0
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or eax, 1 << 31 | 1 << 0 ; Set the PG-bit, which is the 31nd bit, and the PE-bit, which is the 0th bit.
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mov cr0, eax
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; jump to 64-bit longmode
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pop ebx ; restore pointer to multiboot structure
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lgdt [GDT64.Pointer] ; Load the 64-bit global descriptor table.
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jmp GDT64.Code:start64 ; Set the code segment and enter 64-bit long mode.
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[BITS 64]
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start64:
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; initialize segment registers
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mov ax, GDT64.Data
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mov ds, ax
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mov es, ax
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mov fs, ax
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mov gs, ax
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mov ss, ax
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; set default stack pointer
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mov rsp, boot_stack
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add rsp, KERNEL_STACK_SIZE-16
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; interpret multiboot information
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extern multiboot_init
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mov rdi, rbx
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call multiboot_init
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; jump to the boot processors's C code
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extern main
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call main
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jmp $
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%if MAX_CORES > 1
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smp_start64:
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; initialize segment registers
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mov ax, GDT64.Data
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mov ds, ax
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mov es, ax
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mov fs, ax
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mov gs, ax
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mov ss, ax
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; jump to the boot processors's C code
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extern smp_start
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call smp_start
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jmp $
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%endif
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; This will set up our new segment registers and is declared in
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; C as 'extern void gdt_flush();'
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global gdt_flush
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extern gp
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gdt_flush:
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lgdt [gp]
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ret
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; determines the current instruction pointer (after the jmp)
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global read_eip
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read_eip:
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pop rax ; Get the return address
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jmp rax ; Return. Can't use RET because return
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; address popped off the stack.
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; In just a few pages in this tutorial, we will add our Interrupt
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; Service Routines (ISRs) right here!
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global isr0
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global isr1
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global isr2
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global isr3
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global isr4
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global isr5
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global isr6
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global isr7
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global isr8
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global isr9
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global isr10
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global isr11
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global isr12
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global isr13
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global isr14
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global isr15
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global isr16
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global isr17
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global isr18
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global isr19
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global isr20
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global isr21
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global isr22
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global isr23
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global isr24
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global isr25
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global isr26
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global isr27
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global isr28
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global isr29
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global isr30
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global isr31
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global isrsyscall
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; 0: Divide By Zero Exception
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isr0:
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; isr0 - isr31 are registered as "Interrupt Gate"
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; Therefore, the interrupt flag (IF) is already cleared.
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; cli
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push byte 0 ; pseudo error code
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push byte 0
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jmp common_stub
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; 1: Debug Exception
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isr1:
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; isr0 - isr31 are registered as "Interrupt Gate"
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; Therefore, the interrupt flag (IF) is already cleared.
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; cli
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push byte 0 ; pseudo error code
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push byte 1
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jmp common_stub
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; 2: Non Maskable Interrupt Exception
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isr2:
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; isr0 - isr31 are registered as "Interrupt Gate"
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; Therefore, the interrupt flag (IF) is already cleared.
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; cli
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push byte 0 ; pseudo error code
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push byte 2
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jmp common_stub
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; 3: Int 3 Exception
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isr3:
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; isr0 - isr31 are registered as "Interrupt Gate"
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; Therefore, the interrupt flag (IF) is already cleared.
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; cli
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push byte 0 ; pseudo error code
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push byte 3
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jmp common_stub
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; 4: INTO Exception
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isr4:
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; isr0 - isr31 are registered as "Interrupt Gate"
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; Therefore, the interrupt flag (IF) is already cleared.
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; cli
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push byte 0 ; pseudo error code
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push byte 4
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jmp common_stub
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; 5: Out of Bounds Exception
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isr5:
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; isr0 - isr31 are registered as "Interrupt Gate"
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; Therefore, the interrupt flag (IF) is already cleared.
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; cli
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push byte 0 ; pseudo error code
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push byte 5
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jmp common_stub
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; 6: Invalid Opcode Exception
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isr6:
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; isr0 - isr31 are registered as "Interrupt Gate"
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; Therefore, the interrupt flag (IF) is already cleared.
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; cli
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push byte 0 ; pseudo error code
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push byte 6
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jmp common_stub
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; 7: Coprocessor Not Available Exception
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isr7:
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; isr0 - isr31 are registered as "Interrupt Gate"
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; Therefore, the interrupt flag (IF) is already cleared.
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; cli
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push byte 0 ; pseudo error code
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push byte 7
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jmp common_stub
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; 8: Double Fault Exception (With Error Code!)
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isr8:
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; isr0 - isr31 are registered as "Interrupt Gate"
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; Therefore, the interrupt flag (IF) is already cleared.
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; cli
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push byte 8
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jmp common_stub
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; 9: Coprocessor Segment Overrun Exception
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isr9:
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; isr0 - isr31 are registered as "Interrupt Gate"
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; Therefore, the interrupt flag (IF) is already cleared.
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; cli
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push byte 0 ; pseudo error code
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push byte 9
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jmp common_stub
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; 10: Bad TSS Exception (With Error Code!)
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isr10:
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; isr0 - isr31 are registered as "Interrupt Gate"
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; Therefore, the interrupt flag (IF) is already cleared.
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; cli
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push byte 10
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jmp common_stub
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; 11: Segment Not Present Exception (With Error Code!)
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isr11:
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; isr0 - isr31 are registered as "Interrupt Gate"
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; Therefore, the interrupt flag (IF) is already cleared.
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; cli
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push byte 11
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jmp common_stub
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; 12: Stack Fault Exception (With Error Code!)
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isr12:
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; isr0 - isr31 are registered as "Interrupt Gate"
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; Therefore, the interrupt flag (IF) is already cleared.
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; cli
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push byte 12
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jmp common_stub
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; 13: General Protection Fault Exception (With Error Code!)
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isr13:
|
|
; isr0 - isr31 are registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 13
|
|
jmp common_stub
|
|
|
|
; 14: Page Fault Exception (With Error Code!)
|
|
isr14:
|
|
; isr0 - isr31 are registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 14
|
|
jmp common_stub
|
|
|
|
; 15: Reserved Exception
|
|
isr15:
|
|
; isr0 - isr31 are registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 0 ; pseudo error code
|
|
push byte 15
|
|
jmp common_stub
|
|
|
|
; 16: Floating Point Exception
|
|
isr16:
|
|
; isr0 - isr31 are registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 0 ; pseudo error code
|
|
push byte 16
|
|
jmp common_stub
|
|
|
|
; 17: Alignment Check Exception
|
|
isr17:
|
|
; isr0 - isr31 are registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 17
|
|
jmp common_stub
|
|
|
|
; 18: Machine Check Exception
|
|
isr18:
|
|
; isr0 - isr31 are registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 0 ; pseudo error code
|
|
push byte 18
|
|
jmp common_stub
|
|
|
|
; 19: Reserved
|
|
isr19:
|
|
; isr0 - isr31 are registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 0 ; pseudo error code
|
|
push byte 19
|
|
jmp common_stub
|
|
|
|
; 20: Reserved
|
|
isr20:
|
|
; isr0 - isr31 are registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 0 ; pseudo error code
|
|
push byte 20
|
|
jmp common_stub
|
|
|
|
; 21: Reserved
|
|
isr21:
|
|
; isr0 - isr31 are registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 0 ; pseudo error code
|
|
push byte 21
|
|
jmp common_stub
|
|
|
|
; 22: Reserved
|
|
isr22:
|
|
; isr0 - isr31 are registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 0 ; pseudo error code
|
|
push byte 22
|
|
jmp common_stub
|
|
|
|
; 23: Reserved
|
|
isr23:
|
|
; isr0 - isr31 are registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 0 ; pseudo error code
|
|
push byte 23
|
|
jmp common_stub
|
|
|
|
; 24: Reserved
|
|
isr24:
|
|
; isr0 - isr31 are registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 0 ; pseudo error code
|
|
push byte 24
|
|
jmp common_stub
|
|
|
|
; 25: Reserved
|
|
isr25:
|
|
; isr0 - isr31 are registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 0 ; pseudo error code
|
|
push byte 25
|
|
jmp common_stub
|
|
|
|
; 26: Reserved
|
|
isr26:
|
|
; isr0 - isr31 are registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 0 ; pseudo error code
|
|
push byte 26
|
|
jmp common_stub
|
|
|
|
; 27: Reserved
|
|
isr27:
|
|
; isr0 - isr31 are registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 0 ; pseudo error code
|
|
push byte 27
|
|
jmp common_stub
|
|
|
|
; 28: Reserved
|
|
isr28:
|
|
; isr0 - isr31 are registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 0 ; pseudo error code
|
|
push byte 28
|
|
jmp common_stub
|
|
|
|
; 29: Reserved
|
|
isr29:
|
|
; isr0 - isr31 are registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 0 ; pseudo error code
|
|
push byte 29
|
|
jmp common_stub
|
|
|
|
; 30: Reserved
|
|
isr30:
|
|
; isr0 - isr31 are registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 0 ; pseudo error code
|
|
push byte 30
|
|
jmp common_stub
|
|
|
|
; 31: Reserved
|
|
isr31:
|
|
; isr0 - isr31 are registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 0 ; pseudo error code
|
|
push byte 31
|
|
jmp common_stub
|
|
|
|
extern syscall_handler
|
|
|
|
; used to realize system calls
|
|
isrsyscall:
|
|
push r15
|
|
push r14
|
|
push r13
|
|
push r12
|
|
push r11
|
|
push r10
|
|
push r9
|
|
push r8
|
|
push rdi
|
|
push rsi
|
|
push rbp
|
|
push rsp
|
|
push rbx
|
|
push rdx
|
|
push rcx
|
|
push rax
|
|
|
|
mov rdi, rsp
|
|
call syscall_handler
|
|
|
|
pop rax
|
|
pop rcx
|
|
pop rdx
|
|
pop rbx
|
|
add rsp, 8
|
|
pop rbp
|
|
pop rsi
|
|
pop rdi
|
|
pop r8
|
|
pop r9
|
|
pop r10
|
|
pop r11
|
|
pop r12
|
|
pop r13
|
|
pop r14
|
|
iretq
|
|
|
|
global irq0
|
|
global irq1
|
|
global irq2
|
|
global irq3
|
|
global irq4
|
|
global irq5
|
|
global irq6
|
|
global irq7
|
|
global irq8
|
|
global irq9
|
|
global irq10
|
|
global irq11
|
|
global irq12
|
|
global irq13
|
|
global irq14
|
|
global irq15
|
|
global irq16
|
|
global irq17
|
|
global irq18
|
|
global irq19
|
|
global irq20
|
|
global irq21
|
|
global irq22
|
|
global irq23
|
|
global apic_timer
|
|
global apic_lint0
|
|
global apic_lint1
|
|
global apic_error
|
|
global apic_svr
|
|
|
|
; 32: IRQ0
|
|
irq0:
|
|
; irq0 - irq15 are registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 0 ; pseudo error code
|
|
push byte 32
|
|
jmp common_stub
|
|
|
|
; 33: IRQ1
|
|
irq1:
|
|
; irq0 - irq15 are registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 0 ; pseudo error code
|
|
push byte 33
|
|
jmp common_stub
|
|
|
|
; 34: IRQ2
|
|
irq2:
|
|
; irq0 - irq15 are registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 0 ; pseudo error code
|
|
push byte 34
|
|
jmp common_stub
|
|
|
|
; 35: IRQ3
|
|
irq3:
|
|
; irq0 - irq15 are registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 0 ; pseudo error code
|
|
push byte 35
|
|
jmp common_stub
|
|
|
|
; 36: IRQ4
|
|
irq4:
|
|
; irq0 - irq15 are registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 0 ; pseudo error code
|
|
push byte 36
|
|
jmp common_stub
|
|
|
|
; 37: IRQ5
|
|
irq5:
|
|
; irq0 - irq15 are registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 0 ; pseudo error code
|
|
push byte 37
|
|
jmp common_stub
|
|
|
|
; 38: IRQ6
|
|
irq6:
|
|
; irq0 - irq15 are registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 0 ; pseudo error code
|
|
push byte 38
|
|
jmp common_stub
|
|
|
|
; 39: IRQ7
|
|
irq7:
|
|
; irq0 - irq15 are registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 0 ; pseudo error code
|
|
push byte 39
|
|
jmp common_stub
|
|
|
|
; 40: IRQ8
|
|
irq8:
|
|
; irq0 - irq15 are registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 0 ; pseudo error code
|
|
push byte 40
|
|
jmp common_stub
|
|
|
|
; 41: IRQ9
|
|
irq9:
|
|
; irq0 - irq15 are registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 0 ; pseudo error code
|
|
push byte 41
|
|
jmp common_stub
|
|
|
|
; 42: IRQ10
|
|
irq10:
|
|
; irq0 - irq15 are registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 0 ; pseudo error code
|
|
push byte 42
|
|
jmp common_stub
|
|
|
|
; 43: IRQ11
|
|
irq11:
|
|
; irq0 - irq15 are registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 0 ; pseudo error code
|
|
push byte 43
|
|
jmp common_stub
|
|
|
|
; 44: IRQ12
|
|
irq12:
|
|
; irq0 - irq15 are registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 0 ; pseudo error code
|
|
push byte 44
|
|
jmp common_stub
|
|
|
|
; 45: IRQ13
|
|
irq13:
|
|
; irq0 - irq15 are registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 0 ; pseudo error code
|
|
push byte 45
|
|
jmp common_stub
|
|
|
|
; 46: IRQ14
|
|
irq14:
|
|
; irq0 - irq15 are registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 0 ; pseudo error code
|
|
push byte 46
|
|
jmp common_stub
|
|
|
|
; 47: IRQ15
|
|
irq15:
|
|
; irq0 - irq15 are registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 0 ; pseudo error code
|
|
push byte 47
|
|
jmp common_stub
|
|
|
|
; 48: IRQ16
|
|
irq16:
|
|
; irq16 - irq23 are registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 0 ; pseudo error code
|
|
push byte 48
|
|
jmp common_stub
|
|
|
|
; 49: IRQ17
|
|
irq17:
|
|
; irq16- irq23 are registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 0 ; pseudo error code
|
|
push byte 49
|
|
jmp common_stub
|
|
|
|
; 50: IRQ18
|
|
irq18:
|
|
; irq16 - irq23 are registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 0 ; pseudo error code
|
|
push byte 50
|
|
jmp common_stub
|
|
|
|
; 51: IRQ19
|
|
irq19:
|
|
; irq16 - irq23 are registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 0 ; pseudo error code
|
|
push byte 51
|
|
jmp common_stub
|
|
|
|
; 52: IRQ20
|
|
irq20:
|
|
; irq16- irq23 are registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 0 ; pseudo error code
|
|
push byte 52
|
|
jmp common_stub
|
|
|
|
; 53: IRQ21
|
|
irq21:
|
|
; irq16 - irq23 are registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 0 ; error code
|
|
push byte 53
|
|
jmp common_stub
|
|
|
|
; 54: IRQ22
|
|
irq22:
|
|
; irq16- irq23 are registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 0 ; pseudo error code
|
|
push byte 54
|
|
jmp common_stub
|
|
|
|
; 55: IRQ23
|
|
irq23:
|
|
; irq16 - irq23 are registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 0 ; pseudo error code
|
|
push byte 55
|
|
jmp common_stub
|
|
|
|
apic_timer:
|
|
; apic timer is registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 0 ; pseudo error code
|
|
push byte 123
|
|
jmp common_stub
|
|
|
|
apic_lint0:
|
|
; lint0 is registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 0 ; pseudo error code
|
|
push byte 124
|
|
jmp common_stub
|
|
|
|
apic_lint1:
|
|
; lint1 is registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 0 ; pseudo error code
|
|
push byte 125
|
|
jmp common_stub
|
|
|
|
apic_error:
|
|
; LVT error interrupt is registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 0 ; pseudo error code
|
|
push byte 126
|
|
jmp common_stub
|
|
|
|
apic_svr:
|
|
; SVR is registered as "Interrupt Gate"
|
|
; Therefore, the interrupt flag (IF) is already cleared.
|
|
; cli
|
|
push byte 0 ; pseudo error code
|
|
push byte 127
|
|
jmp common_stub
|
|
|
|
extern irq_handler
|
|
extern get_current_stack
|
|
extern finish_task_switch
|
|
|
|
global switch_context
|
|
ALIGN 8
|
|
switch_context:
|
|
; create on the stack a pseudo interrupt
|
|
; afterwards, we switch to the task with iret
|
|
mov rax, rdi ; rdi contains the address to store the old rsp
|
|
push QWORD 0x10 ; SS
|
|
push rsp ; RSP
|
|
add QWORD [rsp], 8*1
|
|
pushf ; RFLAGS
|
|
push QWORD 0x08 ; CS
|
|
push QWORD rollback ; RIP
|
|
push QWORD 0x00 ; Interrupt number
|
|
push QWORD 0x00edbabe ; Error code
|
|
push rax
|
|
push rcx
|
|
push rdx
|
|
push rbx
|
|
push rsp
|
|
push rbp
|
|
push rsi
|
|
push rdi
|
|
push r8
|
|
push r9
|
|
push r10
|
|
push r11
|
|
push r12
|
|
push r13
|
|
push r14
|
|
push r15
|
|
|
|
jmp common_switch
|
|
|
|
ALIGN 8
|
|
rollback:
|
|
ret
|
|
|
|
ALIGN 8
|
|
common_stub:
|
|
push rax
|
|
push rcx
|
|
push rdx
|
|
push rbx
|
|
push rsp
|
|
push rbp
|
|
push rsi
|
|
push rdi
|
|
push r8
|
|
push r9
|
|
push r10
|
|
push r11
|
|
push r12
|
|
push r13
|
|
push r14
|
|
push r15
|
|
|
|
; use the same handler for interrupts and exceptions
|
|
mov rdi, rsp
|
|
call irq_handler
|
|
|
|
cmp rax, 0
|
|
je no_context_switch
|
|
|
|
common_switch:
|
|
mov [rax], rsp ; store old rsp
|
|
call get_current_stack ; get new rsp
|
|
xchg rax, rsp
|
|
|
|
; set task switched flag
|
|
mov rax, cr0
|
|
or eax, 8
|
|
mov cr0, rax
|
|
|
|
; call cleanup code
|
|
call finish_task_switch
|
|
|
|
no_context_switch:
|
|
pop r15
|
|
pop r14
|
|
pop r13
|
|
pop r12
|
|
pop r11
|
|
pop r10
|
|
pop r9
|
|
pop r8
|
|
pop rdi
|
|
pop rsi
|
|
pop rbp
|
|
add rsp, 8
|
|
pop rbx
|
|
pop rdx
|
|
pop rcx
|
|
pop rax
|
|
|
|
add rsp, 16
|
|
iretq
|
|
|
|
SECTION .data
|
|
global boot_stack
|
|
ALIGN 4096
|
|
boot_stack:
|
|
TIMES (MAX_CORES*KERNEL_STACK_SIZE) DB 0xcd
|
|
|
|
SECTION .note.GNU-stack noalloc noexec nowrite progbits
|