2f64a5c772
All MetalSVM drivers guarantee that the input function will be called in the context of the tcpip thread. Therefore, we are able to use ethernet_input/ip_input instead of tcpip_input
830 lines
28 KiB
C
830 lines
28 KiB
C
/*
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* Copyright 2011 Stefan Lankes, Chair for Operating Systems,
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* RWTH Aachen University
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* This file is part of MetalSVM.
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*/
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/*
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* This eMAC driver required at least sccKit 1.4.0 and based on
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* the eMAC Driver Description (section 9.6.5) in the
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* SccKit 1.4.0 User’s Guide (Revision 0.92 Part 9).
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*/
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#include <metalsvm/stddef.h>
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#include <metalsvm/stdio.h>
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#include <metalsvm/string.h>
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#include <metalsvm/processor.h>
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#include <metalsvm/mailbox.h>
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#include <metalsvm/page.h>
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#include <metalsvm/time.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/RCCE.h>
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#include <asm/RCCE_lib.h>
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#include <asm/SCC_API.h>
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#if defined(CONFIG_LWIP) && defined(CONFIG_ROCKCREEK)
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#include <lwip/sys.h>
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#include <lwip/stats.h>
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#include <lwip/netif.h>
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#include <lwip/tcpip.h>
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#include <netif/etharp.h>
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#include <net/rckemac.h>
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/* enables the cache for the receive buffer */
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#define RX_CACHING 1
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#ifdef RX_CACHING
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#define CL1INV asm volatile ( ".byte 0x0f; .byte 0x0a;\n" ) // CL1FLUSHMB
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#else
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#define CL1INV
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#endif
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/* Limits */
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#define BUFFER_ORDER 9
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#define BUFFER_NUM (1 << BUFFER_ORDER)
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#define BUFFER_SIZE (BUFFER_NUM * PAGE_SIZE)
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#define EMAC0 0x01
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#define EMAC1 0x02
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#define EMAC2 0x04
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#define EMAC3 0x08
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#define EMAC_IPCONF 0x3200
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#define EMAC_RX_CONTROL 0x9000
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#define EMAC_TX_CONTROL 0x9900
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/* IP configuration - offsets */
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#define CONFIG_FLOW_CONTROL_ADD 0xC0
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#define TRANSMITTER_ADDRESS 0x80
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#define RECEIVER1_ADDRESS 0x40
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#define CONFIG_ADD 0x100
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#define ADD_FILTER_MOD 0x190
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/* EMAC RX */
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#define EMAC_RX_BUFFER_START_ADDRESS 0x0000
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#define EMAC_RX_BUFFER_READ_OFFSET 0x0100
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#define EMAC_RX_BUFFER_WRITE_OFFSET 0x0200
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#define EMAC_RX_BUFFER_SIZE 0x0300
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#define EMAC_RX_BUFFER_THRESHOLD 0x0400
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#define EMAC_RX_MODE 0x0500
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#define EMAC_RX_NETWORK_PORT_MAC_ADDRESS_HI 0x0600
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#define EMAC_RX_NETWORK_PORT_MAC_ADDRESS_LO 0x0700
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#define EMAC_RX_NETWORK_PORT_ENABLE 0x0800
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/* EMAC TX */
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#define EMAC_TX_BUFFER_START_ADDRESS 0x0000
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#define EMAC_TX_BUFFER_READ_OFFSET 0x0100
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#define EMAC_TX_BUFFER_WRITE_OFFSET 0x0200
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#define EMAC_TX_BUFFER_SIZE 0x0300
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#define EMAC_TX_MODE 0x0400
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#define EMAC_TX_NETWORK_PORT_ENABLE 0x0500
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#if 1
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// Using of LVT0 as interrupt line
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#define EMAC_IRQ_MASK 0x00000002
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#define EMAC_IRQ_NR 4
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#define EMAC_LVT APIC_LVT0
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#define EMAC_IRQ_CONFIG 0
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#else
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// Using of LVT1 as interrupt line
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#define EMAC_IRQ_MASK 0x00000001
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#define EMAC_IRQ_NR 3
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#define EMAC_LVT APIC_LVT1
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#define EMAC_IRQ_CONFIG 1
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#endif
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#define IRQ_STATUS 0xD000
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#define IRQ_MASK 0xD200
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#define IRQ_RESET 0xD400
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#define IRQ_REQUEST 0xD600
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#define IRQ_CONFIG 0xD800
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/* Cache line wrappers */
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#define CLINE_SHIFT 5
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#define CLINE_SIZE (1UL << CLINE_SHIFT)
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#define CLINE_MASK (~(CLINE_SIZE - 1))
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#define CLINE_ALIGN(_x) (((_x) + CLINE_SIZE - 1) & CLINE_MASK)
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#define CLINE_PACKETS(_x) (CLINE_ALIGN(_x) >> CLINE_SHIFT)
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/* Read 16bit from buffer */
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#define U16(_addr) (256 * (*((uint8_t*) (_addr + 1))) + (*((uint8_t*)(_addr))))
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#define MAC_ADDRESS 0x00454D414331ULL
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#define MAC_HI(_x) ((((_x) >> 32)) & 0xFFFF)
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#define MAC_LO(_x) (((_x) ) & 0xFFFFFFFF)
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#define MIN(a, b) (a) < (b) ? (a) : (b)
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static struct netif* mynetif;
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inline static void* memcpy_from_nc(void *dest, const void *src, size_t count)
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{
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int32_t h, i, j, k, l, m;
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asm volatile ("cld;\n\t"
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"1: cmpl $0, %%eax ; je 3f\n\t"
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"movl (%%edi), %%edx\n\t"
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"cmpl $1, %%eax ; je 2f\n\t"
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"movl 32(%%edi), %%edx\n\t"
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"2: movl 0(%%esi), %%ecx\n\t"
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"movl 4(%%esi), %%edx\n\t"
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"movl %%ecx, 0(%%edi)\n\t"
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"movl %%edx, 4(%%edi)\n\t"
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"movl 8(%%esi), %%ecx\n\t"
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"movl 12(%%esi), %%edx\n\t"
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"movl %%ecx, 8(%%edi)\n\t"
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"movl %%edx, 12(%%edi)\n\t"
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"movl 16(%%esi), %%ecx\n\t"
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"movl 20(%%esi), %%edx\n\t"
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"movl %%ecx, 16(%%edi)\n\t"
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"movl %%edx, 20(%%edi)\n\t"
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"movl 24(%%esi), %%ecx\n\t"
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"movl 28(%%esi), %%edx\n\t"
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"movl %%ecx, 24(%%edi)\n\t"
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"movl %%edx, 28(%%edi)\n\t"
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"addl $32, %%esi\n\t"
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"addl $32, %%edi\n\t"
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"dec %%eax ; jmp 1b\n\t"
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"3: movl %%ebx, %%ecx\n\t"
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"movl (%%edi), %%edx\n\t"
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"andl $31, %%ecx\n\t"
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"rep ; movsb\n\t" : "=&a"(h), "=&D"(i), "=&S"(j), "=&b"(k), "=&c"(l), "=&d"(m)
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: "0"(count / 32), "1"(dest), "2"(src), "3"(count) : "memory","cc");
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return dest;
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}
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inline static void* memcpy_to_nc(void* dest, const void *src, size_t count)
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{
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int32_t i, j, k;
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asm volatile (
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"cld; rep movsl\n\t"
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"movl %4, %%ecx\n\t"
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"andl $3, %%ecx\n\t"
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"rep movsb\n\t"
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: "=&c"(i), "=&D"(j), "=&S"(k)
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: "0"(count/4), "g"(count), "1"(dest), "2"(src) : "memory","cc");
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return dest;
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}
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static int read_emac(int num_emac, int offset, int core)
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{
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int ret;
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ret = *((volatile int*) (FPGA_BASE + num_emac * 0x1000 + offset + core * 4));
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/* no error: read twice, as xilinx ip need some time... */
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ret = *((volatile int*) (FPGA_BASE + num_emac * 0x1000 + offset + core * 4));
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return ret;
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}
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static void write_emac(int num_emac, int offset, int core, int value)
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{
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*((volatile int*) (FPGA_BASE + num_emac * 0x1000 + offset + core * 4)) = value;
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}
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/*
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* @return error code
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* - ERR_OK: packet transferred to hardware
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* - ERR_CONN: no link or link failure
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* - ERR_IF: could not transfer to link (hardware buffer full?)
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*/
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static err_t rckemacif_output(struct netif* netif, struct pbuf* p)
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{
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rckemacif_t* rckemacif = netif->state;
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uint32_t i;
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struct pbuf *q;
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void *addr;
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uint16_t read_offset;
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int rest;
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int packets;
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int sum = 0;
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int chance = 20;
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/* check for over/underflow */
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if (BUILTIN_EXPECT((p->tot_len < 20 /* IP header size */) || (p->tot_len > 1536), 0)) {
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LWIP_DEBUGF(NETIF_DEBUG, ("rckemacif_output: illegal packet length %d => drop\n", p->tot_len));
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return ERR_IF;
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}
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rckemacif->tx_write_offset++;
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/* check if we need to wrap */
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if (rckemacif->tx_write_offset > rckemacif->tx_buffer_max)
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rckemacif->tx_write_offset = 1;
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packets = CLINE_PACKETS(p->tot_len + 2);
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//LWIP_DEBUGF(NETIF_DEBUG, ("TX packets: %d\n", packets));
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read_offset = read_emac(rckemacif->num_emac, EMAC_TX_CONTROL+EMAC_TX_BUFFER_READ_OFFSET, rckemacif->core);
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#if 1
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again:
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if (read_offset < rckemacif->tx_write_offset)
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sum = rckemacif->tx_buffer_max - rckemacif->tx_write_offset + read_offset - 1;
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else if (read_offset > rckemacif->tx_write_offset)
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sum = read_offset - rckemacif->tx_write_offset - 1;
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if (sum < packets) {
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LWIP_DEBUGF(NETIF_DEBUG, ("Warning: not enough space available, retrying...\n"));
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chance--;
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if (chance < 0)
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return ERR_MEM;
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goto again;
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}
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#endif
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addr = rckemacif->tx_buffer + rckemacif->tx_write_offset * 32;
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/* Set frame length */
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((uint8_t*)addr)[0] = p->tot_len % 256;
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((uint8_t*)addr)[1] = p->tot_len / 256;
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#if ETH_PAD_SIZE
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pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */
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#endif
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if (rckemacif->tx_write_offset + packets - 1 <= rckemacif->tx_buffer_max) {
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/*
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* q traverses through linked list of pbuf's
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* This list MUST consist of a single packet ONLY
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*/
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for (q=p, i=0; q!=0; q=q->next) {
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memcpy_to_nc(((uint8_t*)addr) + 2 + i, q->payload, q->len);
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i += q->len;
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}
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/* increment write ptr */
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rckemacif->tx_write_offset += packets - 1;
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} else {
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/* wrap in offsets. first copy to the end, second at the starting
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* point
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*/
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int bytes_left = p->tot_len;
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int bytes_to_copy = (rckemacif->tx_buffer_max - rckemacif->tx_write_offset + 1) * 32 - 2;
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int sz = 0;
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if (bytes_left < bytes_to_copy)
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bytes_to_copy = bytes_left;
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//LWIP_DEBUGF(NETIF_DEBUG, ("special case: copy last %d bytes\n", bytes_to_copy));
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q = p; i = 0;
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while ((q != 0) && (i < bytes_to_copy)) {
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sz = MIN(bytes_to_copy-i, q->len);
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memcpy_to_nc(((uint8_t*) addr) + 2 + i, q->payload, sz);
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bytes_left -= sz;
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i += sz;
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if (i < bytes_to_copy)
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q = q->next;
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}
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if (bytes_left != 0) {
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rckemacif->tx_write_offset = 1;
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addr = rckemacif->tx_buffer + 32;
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//LWIP_DEBUGF(NETIF_DEBUG, ("special case: copy remaining %d bytes\n", bytes_left));
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i = 0;
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if (sz < q->len) {
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memcpy_to_nc((uint8_t*) addr, q->payload + sz, q->len - sz);
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i = q->len - sz;
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}
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for(q=q->next; (q != 0); q = q->next) {
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memcpy_to_nc(((uint8_t*) addr) + i, q->payload, q->len);
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i += q->len;
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}
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rest = bytes_left % 32;
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if (rest != 0)
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rest = 32 - rest;
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//LWIP_DEBUGF(NETIF_DEBUG, ("Rest is %d\n", rest));
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rckemacif->tx_write_offset += CLINE_PACKETS(bytes_left + rest) - 1;
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}
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}
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*((volatile int*) rckemacif->tx_buffer) = 2;
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// flush write combining buffers
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*((int*)RCCE_fool_write_combine_buffer) = 1;
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/* set new write offset */
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//LWIP_DEBUGF(NETIF_DEBUG, ("Update tx write offset: %d (read offset %d)\n", rckemacif->tx_write_offset, read_offset));
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write_emac(rckemacif->num_emac, EMAC_TX_CONTROL+EMAC_TX_BUFFER_WRITE_OFFSET, rckemacif->core, rckemacif->tx_write_offset);
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#if ETH_PAD_SIZE
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pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */
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#endif
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LINK_STATS_INC(link.xmit);
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return ERR_OK;
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}
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static void rckemacif_rx_handler(struct netif* netif, unsigned int write_offset)
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{
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rckemacif_t* rckemacif = netif->state;
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unsigned short read_offset = rckemacif->rx_read_offset;
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volatile void *addr = NULL;
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uint16_t i, length = 0;
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struct pbuf *p = NULL;
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struct pbuf* q;
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if (write_offset > rckemacif->rx_buffer_max) {
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LWIP_DEBUGF(NETIF_DEBUG, ("Warning, write offset > buffer max!! (%d > %d)\n", write_offset, rckemacif->rx_buffer_max));
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read_offset = 1;
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goto rxDone;
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}
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again:
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CL1INV; // invalidate L1 cache entries of the receiver buffers
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read_offset++;
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if (read_offset < 1 || read_offset > rckemacif->rx_buffer_max) {
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read_offset = 1;
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}
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addr = rckemacif->rx_buffer + read_offset * 32;
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length = U16(addr);
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// Check for over/underflow
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if (BUILTIN_EXPECT((length < 20) || (length > 1536), 0)) {
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LWIP_DEBUGF(NETIF_DEBUG, ("rckemacif_rx_handler(): illegal packet length %d => drop\n", length));
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LWIP_DEBUGF(NETIF_DEBUG, ("start read at %d; write_offset at %d; addr: %p, packet len: %d\n", read_offset, write_offset, addr, length));
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read_offset = write_offset;
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#if 1
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kprintf("Buffer:\n");
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for (i = 0; i < 32; i++) {
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kprintf("%2.2x ", ((char*)addr)[i] & 0xFF);
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}
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kprintf("\n");
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kprintf("Buffer0:\n");
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for (i = 0; i < 32; i++) {
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kprintf("%2.2x ", ((char*)rckemacif->rx_buffer)[i] & 0xFF);
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}
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kprintf("\n");
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#endif
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LINK_STATS_INC(link.memerr);
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LINK_STATS_INC(link.drop);
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goto rxDone;
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}
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#if ETH_PAD_SIZE
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length += ETH_PAD_SIZE; /* allow room for Ethernet padding */
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#endif
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//LWIP_DEBUGF(NETIF_DEBUG, ("length %u, read_offset %u, write_offset %u\n", length, read_offset, write_offset));
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p = pbuf_alloc(PBUF_RAW, length, PBUF_POOL);
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if (BUILTIN_EXPECT(p != NULL, 1)) {
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#if ETH_PAD_SIZE
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pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */
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#endif
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if (read_offset < write_offset) {
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unsigned int counter;
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for (q=p, counter=0; q!=NULL; q=q->next) {
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memcpy_from_nc((uint8_t*) q->payload, (uint8_t*)addr + 2 + counter, q->len);
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counter += q->len;
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}
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read_offset += CLINE_PACKETS(p->tot_len + 2) - 1;
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} else {
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int rest;
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int bytesLeft = length;
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int bytesToCopy = length;
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int counter = 0;
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/* rest to the end of buffer - 2 bytes length information */
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rest = (rckemacif->rx_buffer_max - read_offset + 1) * 32 - 2;
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if (length > rest)
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bytesToCopy = rest;
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//LWIP_DEBUGF(NETIF_DEBUG, ("bytes to copy: %d, bytesLeft: %d\n", bytesToCopy, bytesLeft));
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q = p;
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i = 0;
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while ((q != NULL) && (counter < bytesToCopy)) {
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i = MIN(q->len, bytesToCopy - counter);
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memcpy_from_nc(q->payload, (uint8_t*) addr + 2 + counter, i);
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counter += i;
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if (counter >= bytesToCopy)
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goto out;
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else
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q = q->next;
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}
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out:
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bytesLeft -= bytesToCopy;
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if (bytesLeft != 0) {
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addr = rckemacif->rx_buffer + 0x20;
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counter = 0;
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//LWIP_DEBUGF(NETIF_DEBUG, ("copying from %p, left: %d (%x)\n", addr, bytesLeft, ((uint8_t*)addr)[0]));
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if (i < q->len) {
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counter = MIN(q->len - i, bytesLeft);
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memcpy_from_nc((uint8_t*)q->payload + i, (uint8_t*) addr, counter);
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}
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for(q=q->next; (q!=NULL) && (counter < bytesLeft); q=q->next) {
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i = MIN(q->len, bytesLeft - counter);
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memcpy_from_nc((uint8_t*)q->payload, (uint8_t*)addr + counter, i);
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counter += i;
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}
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read_offset = CLINE_PACKETS(bytesLeft);
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} else {
|
||
read_offset += CLINE_PACKETS(p->tot_len + 2) - 1;
|
||
}
|
||
}
|
||
|
||
#if ETH_PAD_SIZE
|
||
pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */
|
||
#endif
|
||
LINK_STATS_INC(link.recv);
|
||
} else {
|
||
LWIP_DEBUGF(NETIF_DEBUG, ("rckemacif_rx_inthandler: not enough memory!\n"));
|
||
LINK_STATS_INC(link.memerr);
|
||
LINK_STATS_INC(link.drop);
|
||
}
|
||
|
||
rxDone:
|
||
/* set new read pointer */
|
||
//LWIP_DEBUGF(NETIF_DEBUG, ("Update rx read offset: %d\n", read_offset));
|
||
write_emac(rckemacif->num_emac, EMAC_RX_CONTROL + EMAC_RX_BUFFER_READ_OFFSET, rckemacif->core, read_offset);
|
||
rckemacif->rx_read_offset = read_offset;
|
||
|
||
if (p) {
|
||
netif->input(p, netif);
|
||
p = NULL;
|
||
}
|
||
|
||
if (read_offset != write_offset)
|
||
goto again;
|
||
|
||
/* Enable eMAC interrupt */
|
||
unsigned int tmp = *((volatile unsigned int*) (FPGA_BASE + IRQ_MASK + rckemacif->core * 2 * 4));
|
||
// read twice to be sure
|
||
tmp = *((volatile unsigned int*) (FPGA_BASE + IRQ_MASK + rckemacif->core * 2 * 4));
|
||
*((volatile unsigned int*) (FPGA_BASE + IRQ_MASK + rckemacif->core * 2 * 4)) = tmp & ~(1 << rckemacif->num_emac);
|
||
rckemacif->polling = 0;
|
||
}
|
||
|
||
/* this function is called in the context of the tcpip thread */
|
||
static void rckemacif_poll(void* ctx)
|
||
{
|
||
unsigned int write_offset = (unsigned int) ctx;
|
||
|
||
rckemacif_rx_handler(mynetif, write_offset);
|
||
}
|
||
|
||
void rckemacif_handler(struct state* s, uint32_t status)
|
||
{
|
||
unsigned int write_offset;
|
||
rckemacif_t* rckemacif = mynetif->state;
|
||
|
||
if (!(status & (1 << rckemacif->num_emac)))
|
||
return;
|
||
|
||
/* check for updated write offset */
|
||
write_offset = *((volatile unsigned int*) (rckemacif->rx_buffer)) & 0xFFFF;
|
||
//write_offset = read_emac(rckemacif->num_emac, EMAC_RX_CONTROL + EMAC_RX_BUFFER_WRITE_OFFSET, rckemacif->core);
|
||
if ((write_offset != 0) && (rckemacif->rx_read_offset != write_offset) && !rckemacif->polling) {
|
||
#if NO_SYS
|
||
rckemacif_poll((void*) write_offset);
|
||
#else
|
||
if (tcpip_callback_with_block(rckemacif_poll, (void*) write_offset, 0) == ERR_OK) {
|
||
/* Mask eMAC interrupt */
|
||
unsigned int tmp = *((volatile unsigned int*) (FPGA_BASE + IRQ_MASK + rckemacif->core * 2 * 4));
|
||
// read twice to be sure
|
||
tmp = *((volatile unsigned int*) (FPGA_BASE + IRQ_MASK + rckemacif->core * 2 * 4));
|
||
*((volatile unsigned int*) (FPGA_BASE + IRQ_MASK + rckemacif->core * 2 * 4)) = tmp | (1 << rckemacif->num_emac);
|
||
rckemacif->polling = 1;
|
||
} else {
|
||
LWIP_DEBUGF(NETIF_DEBUG, ("rckemacif_handler: unable to send a poll request to the tcpip thread\n"));
|
||
}
|
||
#endif
|
||
}
|
||
}
|
||
|
||
err_t rckemacif_init(struct netif* netif)
|
||
{
|
||
rckemacif_t* rckemacif;
|
||
int num_emac;
|
||
int macPorts;
|
||
int i, tmp, x, y, z, core;
|
||
uint64_t tile_offset;
|
||
uint16_t write_offset;
|
||
uint16_t read_offset;
|
||
int mode;
|
||
int subdest;
|
||
int route;
|
||
|
||
LWIP_DEBUGF(NETIF_DEBUG, ("Initialize eMAC device...\n"));
|
||
|
||
LWIP_ASSERT("netif != NULL", (netif != NULL));
|
||
|
||
// Find out who I am...
|
||
tmp = ReadConfigReg(CRB_OWN+MYTILEID);
|
||
x = (tmp>>3) & 0x0f; // bits 06:03
|
||
y = (tmp>>7) & 0x0f; // bits 10:07
|
||
z = (tmp ) & 0x07; // bits 02:00
|
||
core = 12 * y + 2 * x + z;
|
||
|
||
rckemacif = kmalloc(sizeof(rckemacif_t));
|
||
if (!rckemacif) {
|
||
LWIP_DEBUGF(NETIF_DEBUG, ("rckemacif_init: out of memory\n"));
|
||
return ERR_MEM;
|
||
}
|
||
memset(rckemacif, 0x00, sizeof(rckemacif_t));
|
||
rckemacif->core = core;
|
||
|
||
/* allocate the receive buffer */
|
||
#ifdef RX_CACHING
|
||
rckemacif->rx_buffer = mem_allocation(BUFFER_SIZE, MAP_KERNEL_SPACE|MAP_MPE);
|
||
#else
|
||
rckemacif->rx_buffer = mem_allocation(BUFFER_SIZE, MAP_KERNEL_SPACE|MAP_NO_CACHE);
|
||
#endif
|
||
if (!(rckemacif->rx_buffer)) {
|
||
LWIP_DEBUGF(NETIF_DEBUG, ("rckemacif_init: out of memory\n"));
|
||
kfree(rckemacif, sizeof(rckemacif_t));
|
||
return ERR_MEM;
|
||
}
|
||
memset(rckemacif->rx_buffer, 0x00, 0x20);
|
||
memset(rckemacif->rx_buffer + 0x20, 0xDA, BUFFER_SIZE - 0x20);
|
||
rckemacif->rx_buffer_max = CLINE_PACKETS(BUFFER_SIZE) - 1;
|
||
|
||
/* allocate the send buffers */
|
||
rckemacif->tx_buffer = mem_allocation(BUFFER_SIZE, MAP_KERNEL_SPACE|MAP_NO_CACHE|MAP_WT|MAP_MPE);
|
||
if (!(rckemacif->tx_buffer)) {
|
||
LWIP_DEBUGF(NETIF_DEBUG, ("rckemacif_init: out of memory\n"));
|
||
kfree(rckemacif->rx_buffer, BUFFER_SIZE);
|
||
kfree(rckemacif, sizeof(rckemacif_t));
|
||
return ERR_MEM;
|
||
}
|
||
memset(rckemacif->tx_buffer, 0x00, 0x20);
|
||
memset(rckemacif->tx_buffer + 0x20, 0xDA, BUFFER_SIZE - 0x20);
|
||
rckemacif->tx_buffer_max = CLINE_PACKETS(BUFFER_SIZE) - 1;
|
||
netif->state = rckemacif;
|
||
|
||
/* Depending on core location read own private data
|
||
* (offset, subdest, route)
|
||
*/
|
||
tmp = z == 0 ? ReadConfigReg(CRB_OWN + LUT0) : ReadConfigReg(CRB_OWN + LUT1);
|
||
tile_offset = (uint64_t)((uint64_t) tmp & 0x3FF) << 24;
|
||
subdest = (tmp >> 10) & 0x07;
|
||
route = (tmp >> 13) & 0xFF;
|
||
mode = (subdest << 8) + route;
|
||
LWIP_DEBUGF(NETIF_DEBUG, ("tile_offset = 0x%llx\n", tile_offset));
|
||
|
||
/* get fpga/sccKit port settings */
|
||
tmp = *((volatile int*)(FPGA_BASE + 0x822C));
|
||
tmp = *((volatile int*)(FPGA_BASE + 0x822C));
|
||
macPorts = ((tmp >> 9 ) & 0xFF);
|
||
|
||
LWIP_DEBUGF(NETIF_DEBUG, ("rckemacif_init: eMAC0: %s eMAC1: %s eMAC2: %s eMAC3: %s\n",
|
||
(macPorts & EMAC0) != 0 ? "present" : "-",
|
||
(macPorts & EMAC1) != 0 ? "present" : "-",
|
||
(macPorts & EMAC2) != 0 ? "present" : "-",
|
||
(macPorts & EMAC3) != 0 ? "present" : "-"));
|
||
|
||
// determine device and emac number
|
||
num_emac=0;
|
||
while (((macPorts & (1 << num_emac)) == 0) && (num_emac < 4))
|
||
num_emac++;
|
||
if (num_emac >= 4)
|
||
return ERR_ARG;
|
||
mynetif = netif;
|
||
rckemacif->num_emac = num_emac;
|
||
|
||
LWIP_DEBUGF(NETIF_DEBUG, ("rckemacif_init: used eMAC device %d\n", num_emac));
|
||
|
||
tmp = read_emac(num_emac, EMAC_IPCONF+TRANSMITTER_ADDRESS, 0);
|
||
tmp = read_emac(num_emac, EMAC_IPCONF+RECEIVER1_ADDRESS, 0);
|
||
|
||
if (core == 0) {
|
||
/* Only core 0 initialize the xilinx port */
|
||
int flow_control = 0;
|
||
int transmitter_addr = 0;
|
||
int receiver1_addr = 0;
|
||
int config_add = 0;
|
||
int add_filter_mod = 0;
|
||
|
||
/* Disable tx and rx flow control of eMAC */
|
||
LWIP_DEBUGF(NETIF_DEBUG, ("Disabling tx/rx flow control of eMAC%d\n", num_emac));
|
||
flow_control = read_emac(num_emac, EMAC_IPCONF+CONFIG_FLOW_CONTROL_ADD, 0);
|
||
|
||
/* Set top 3 bits of the flow control configuration to zero,
|
||
* therefore disabling tx and rx flow control
|
||
*/
|
||
flow_control &= 0x7FFFFFF;
|
||
write_emac(num_emac, EMAC_IPCONF+CONFIG_FLOW_CONTROL_ADD, 0, flow_control);
|
||
|
||
/* Sanity check */
|
||
flow_control = read_emac(num_emac, EMAC_IPCONF+CONFIG_FLOW_CONTROL_ADD, 0);
|
||
LWIP_DEBUGF(NETIF_DEBUG, (" CONFIG_FLOW_CONTROL_ADD set: 0x%x\n", flow_control));
|
||
|
||
/* Setting the tx configuration bit to enable the transmitter and
|
||
* set to full duplex mode.
|
||
*/
|
||
LWIP_DEBUGF(NETIF_DEBUG, ("Setting rx configuration of eMAC%d\n", num_emac));
|
||
transmitter_addr = read_emac(num_emac, EMAC_IPCONF+TRANSMITTER_ADDRESS, 0);
|
||
|
||
/* Now set the relevant bits and write back into the register:
|
||
* 26 (half duplex) = 0, 28 (transmit enable) = 1, 31 (reset) = 0
|
||
*/
|
||
transmitter_addr &= ~(1 << 31);
|
||
transmitter_addr &= ~(1 << 26);
|
||
transmitter_addr |= (1 << 28);
|
||
write_emac(num_emac, EMAC_IPCONF+TRANSMITTER_ADDRESS, 0, transmitter_addr);
|
||
|
||
transmitter_addr = read_emac(num_emac, EMAC_IPCONF+TRANSMITTER_ADDRESS, 0);
|
||
LWIP_DEBUGF(NETIF_DEBUG, (" TRANSMITTER_ADDRESS set: %x\n", transmitter_addr));
|
||
|
||
/* Setting the rx configuration bit to enable the transmitter and
|
||
* set to full duplex mode.
|
||
*/
|
||
LWIP_DEBUGF(NETIF_DEBUG, ("Setting IP configuration of EMAC%d\n", num_emac));
|
||
|
||
/* Read the current config value from the register */
|
||
receiver1_addr = read_emac(num_emac, EMAC_IPCONF+RECEIVER1_ADDRESS, 0);
|
||
|
||
/* Now set the relevant bits and write back into the register:
|
||
* 25 = 1, 26 = 0, 28 = 1, 31 = 0
|
||
*/
|
||
/* Length/Type Error Check Disable */
|
||
receiver1_addr |= (1 << 25);
|
||
/* Disable Half Duplex => Full Duplex */
|
||
receiver1_addr &= ~(1 << 26);
|
||
/* Receiver enable */
|
||
receiver1_addr |= (1 << 28);
|
||
/* Reset */
|
||
receiver1_addr &= ~(1 << 31);
|
||
write_emac(num_emac, EMAC_IPCONF+RECEIVER1_ADDRESS, 0, receiver1_addr);
|
||
|
||
receiver1_addr = read_emac(num_emac, EMAC_IPCONF+RECEIVER1_ADDRESS, 0);
|
||
LWIP_DEBUGF(NETIF_DEBUG, (" RECEIVER1_ADDRESS set: %x\n", receiver1_addr));
|
||
|
||
/* Setting the speed to eMAC to 1Gb/s */
|
||
LWIP_DEBUGF(NETIF_DEBUG, ("Setting speed of EMAC%d to 1Gb/s\n", num_emac));
|
||
|
||
/* Read the current config value from register */
|
||
config_add = read_emac(num_emac, EMAC_IPCONF+CONFIG_ADD, 0);
|
||
|
||
/* Now set the relevant bits and write back into the register:
|
||
* 31 = 1, 30 = 0
|
||
*/
|
||
/* MAC Speed Configuration: 00 - 10Mbps, 01 - 100Mbps, 10 - 1Gbps */
|
||
config_add |= (1 << 31);
|
||
config_add &= ~(1 << 30);
|
||
write_emac(num_emac, EMAC_IPCONF+CONFIG_ADD, 0, config_add);
|
||
|
||
config_add = read_emac(num_emac, EMAC_IPCONF+CONFIG_ADD, 0);
|
||
LWIP_DEBUGF(NETIF_DEBUG, (" CONFIG_ADD set: %x\n", config_add));
|
||
|
||
/* Read the current config addr filter mode */
|
||
add_filter_mod = read_emac(num_emac, EMAC_IPCONF+ADD_FILTER_MOD, 0);
|
||
|
||
/* Not set the relevant bits and write back into the register:
|
||
* 31 (promiscuous mode) = 1 not working, but thats ok!
|
||
*/
|
||
add_filter_mod |= (1 << 31);
|
||
write_emac(num_emac, EMAC_IPCONF+ADD_FILTER_MOD, 0, add_filter_mod);
|
||
|
||
add_filter_mod = read_emac(num_emac, EMAC_IPCONF+ADD_FILTER_MOD, 0);
|
||
LWIP_DEBUGF(NETIF_DEBUG, (" ADD_FILTER_MOD set: %x\n", add_filter_mod));
|
||
}
|
||
|
||
RCCE_barrier(&RCCE_COMM_WORLD);
|
||
|
||
/* Start address */
|
||
LWIP_DEBUGF(NETIF_DEBUG, (" RX Buffer %p (%lx phys)\n", rckemacif->rx_buffer, virt_to_phys((uint32_t)rckemacif->rx_buffer)));
|
||
|
||
/**** Receiver configuration ****/
|
||
|
||
uint64_t addr_offset = (tile_offset + (uint64_t) virt_to_phys((uint32_t) rckemacif->rx_buffer)) >> 5;
|
||
write_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_BUFFER_START_ADDRESS, core, (uint32_t) addr_offset);
|
||
LWIP_DEBUGF(NETIF_DEBUG, (" RX Buffer set to @%x\n", read_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_BUFFER_START_ADDRESS, core)));
|
||
|
||
/* Get buffer write offset */
|
||
write_offset = read_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_BUFFER_WRITE_OFFSET, core);
|
||
LWIP_DEBUGF(NETIF_DEBUG, (" RX Buffer write offset at: %d\n", write_offset));
|
||
|
||
/* Set buffer read offset to write offset */
|
||
write_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_BUFFER_READ_OFFSET, core, write_offset);
|
||
LWIP_DEBUGF(NETIF_DEBUG, (" RX Buffer read offset set to: %d\n", read_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_BUFFER_READ_OFFSET, core)));
|
||
rckemacif->rx_read_offset = write_offset;
|
||
|
||
/* Size */
|
||
write_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_BUFFER_SIZE, core, rckemacif->rx_buffer_max);
|
||
LWIP_DEBUGF(NETIF_DEBUG, (" RX Size set to %d\n", read_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_BUFFER_SIZE, core)));
|
||
|
||
/* Threshold */
|
||
write_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_BUFFER_THRESHOLD, core, 0x01);
|
||
LWIP_DEBUGF(NETIF_DEBUG, (" RX Threshold set to %x\n", read_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_BUFFER_THRESHOLD, core)));
|
||
|
||
/* Route */
|
||
write_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_MODE, core, (z << 24) | (((y << 4) | x) << 16) | mode);
|
||
LWIP_DEBUGF(NETIF_DEBUG, (" RX Mode set to %x\n", read_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_MODE, core)));
|
||
|
||
// determine mac address
|
||
uint32_t mac1 = *((volatile uint32_t*)(FPGA_BASE+0x7E00));
|
||
uint32_t mac2 = *((volatile uint32_t*)(FPGA_BASE+0x7E04));
|
||
uint64_t mac = (((unsigned long long)mac1) << 32) + (unsigned long long) mac2;
|
||
if (mac == 0x00)
|
||
mac = MAC_ADDRESS;
|
||
/* Calculate mac address of core depending on selected emac device */
|
||
mac = mac + (1 << num_emac) * 0x100 + core;
|
||
|
||
for (i=0; i<6; i++)
|
||
mynetif->hwaddr[5-i] = (mac >> (i*8)) & 0xFF;
|
||
LWIP_DEBUGF(NETIF_DEBUG, ("rckemacif_init: MAC address "));
|
||
for (i=0; i<6; i++)
|
||
LWIP_DEBUGF(NETIF_DEBUG, ("%02x ", mynetif->hwaddr[i]));
|
||
LWIP_DEBUGF(NETIF_DEBUG, ("\n"));
|
||
|
||
write_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_NETWORK_PORT_MAC_ADDRESS_HI, core, MAC_HI(mac));
|
||
LWIP_DEBUGF(NETIF_DEBUG, (" MAC1 set to %x\n", read_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_NETWORK_PORT_MAC_ADDRESS_HI, core)));
|
||
write_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_NETWORK_PORT_MAC_ADDRESS_LO, core, MAC_LO(mac));
|
||
LWIP_DEBUGF(NETIF_DEBUG, (" MAC2 set to %x\n", read_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_NETWORK_PORT_MAC_ADDRESS_LO, core)));
|
||
|
||
/* Activate network port by setting enable bit */
|
||
write_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_NETWORK_PORT_ENABLE, core, 0x01);
|
||
LWIP_DEBUGF(NETIF_DEBUG, (" RX Port enable set to %x\n", read_emac(num_emac, EMAC_RX_CONTROL + EMAC_RX_NETWORK_PORT_ENABLE, core)));
|
||
|
||
/**** Transfer configuration ****/
|
||
|
||
/* Start address */
|
||
LWIP_DEBUGF(NETIF_DEBUG, (" TX Buffer %p (%lx phys)\n", rckemacif->tx_buffer, virt_to_phys((uint32_t)rckemacif->tx_buffer)));
|
||
write_emac(num_emac, EMAC_TX_CONTROL + EMAC_TX_BUFFER_START_ADDRESS, core, (uint32_t) (((uint64_t) virt_to_phys((uint32_t)rckemacif->tx_buffer) + tile_offset) >> 5));
|
||
LWIP_DEBUGF(NETIF_DEBUG, (" TX Buffer set to @%x\n", read_emac(num_emac, EMAC_TX_CONTROL + EMAC_TX_BUFFER_START_ADDRESS, core)));
|
||
|
||
/* Get buffer read offset */
|
||
read_offset = read_emac(num_emac, EMAC_TX_CONTROL + EMAC_TX_BUFFER_READ_OFFSET, core);
|
||
LWIP_DEBUGF(NETIF_DEBUG, (" TX Buffer read offset at: %d\n", read_offset));
|
||
|
||
/* Set buffer write offset to read offset */
|
||
write_emac(num_emac, EMAC_TX_CONTROL + EMAC_TX_BUFFER_WRITE_OFFSET, core, read_offset);
|
||
LWIP_DEBUGF(NETIF_DEBUG, (" TX Buffer write offset set to: %d\n", read_emac(num_emac, EMAC_TX_CONTROL+ EMAC_TX_BUFFER_WRITE_OFFSET, core)));
|
||
rckemacif->tx_write_offset = read_offset;
|
||
|
||
/* Size */
|
||
write_emac(num_emac, EMAC_TX_CONTROL + EMAC_TX_BUFFER_SIZE, core, rckemacif->tx_buffer_max);
|
||
LWIP_DEBUGF(NETIF_DEBUG, (" TX Size set to %d\n", read_emac(num_emac, EMAC_TX_CONTROL + EMAC_TX_BUFFER_SIZE, core)));
|
||
|
||
/* Route */
|
||
write_emac(num_emac, EMAC_TX_CONTROL + EMAC_TX_MODE, core, mode);
|
||
LWIP_DEBUGF(NETIF_DEBUG, (" TX Mode set to %x\n", read_emac(num_emac, EMAC_TX_CONTROL + EMAC_TX_MODE, core)));
|
||
|
||
/* Activate network port by setting enable bit */
|
||
write_emac(num_emac, EMAC_TX_CONTROL + EMAC_TX_NETWORK_PORT_ENABLE, core, 0x01);
|
||
LWIP_DEBUGF(NETIF_DEBUG, (" TX Port enable set to %x\n", read_emac(num_emac, EMAC_TX_CONTROL + EMAC_TX_NETWORK_PORT_ENABLE, core)));
|
||
|
||
/* Enable interrupt */
|
||
*((volatile unsigned int*) (FPGA_BASE + IRQ_MASK + core * 8)) &= ~(1 << num_emac);
|
||
//*((volatile unsigned int*) (FPGA_BASE + IRQ_CONFIG + core * 4)) = EMAC_IRQ_CONFIG;
|
||
LWIP_DEBUGF(NETIF_DEBUG, (" IRQ_MASK set to 0x%x\n", *((volatile unsigned int*) (FPGA_BASE + IRQ_MASK + core * 8))));
|
||
//LWIP_DEBUGF(NETIF_DEBUG, (" IRQ_CONFIG set to 0x%x\n", *((volatile unsigned int*) (FPGA_BASE + IRQ_CONFIG + core * 8))));
|
||
|
||
/*
|
||
* Initialize the snmp variables and counters inside the struct netif.
|
||
* The last argument should be replaced with your link speed, in units
|
||
* of bits per second.
|
||
*/
|
||
NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, 1000 /* speed */);
|
||
|
||
/* administrative details */
|
||
netif->name[0] = 'e';
|
||
netif->name[1] = 'n';
|
||
netif->num = 0;
|
||
/* downward functions */
|
||
netif->output = etharp_output;
|
||
netif->linkoutput = rckemacif_output;
|
||
/* maximum transfer unit */
|
||
netif->mtu = 1500;
|
||
/* broadcast capability */
|
||
netif->flags |= NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP;
|
||
/* hardware address length */
|
||
netif->hwaddr_len = 6;
|
||
|
||
rckemacif->ethaddr = (struct eth_addr *)netif->hwaddr;
|
||
|
||
// flush write combining buffers
|
||
*(int *)RCCE_fool_write_combine_buffer = 1;
|
||
|
||
return ERR_OK;
|
||
}
|
||
#endif
|