838 lines
21 KiB
C
838 lines
21 KiB
C
/*
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* Copyright 2010 Stefan Lankes, Chair for Operating Systems,
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* RWTH Aachen University
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* This file is part of MetalSVM.
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*/
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#include <metalsvm/stddef.h>
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#include <metalsvm/stdio.h>
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#include <metalsvm/stdlib.h>
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#include <metalsvm/string.h>
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#include <metalsvm/errno.h>
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#include <metalsvm/processor.h>
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#include <metalsvm/time.h>
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#include <metalsvm/init.h>
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#include <metalsvm/page.h>
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#include <metalsvm/spinlock.h>
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#include <metalsvm/mmu.h>
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#include <metalsvm/tasks.h>
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#include <asm/irq.h>
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#include <asm/idt.h>
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#include <asm/irqflags.h>
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#include <asm/apic.h>
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#include <asm/multiboot.h>
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#ifdef CONFIG_ROCKCREEK
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#include <asm/RCCE_lib.h>
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#endif
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#if defined(CONFIG_ROCKCREEK) && (MAX_CORES > 1)
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#error RockCreek is not a SMP system
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#endif
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// IO APIC MMIO structure: write reg, then read or write data.
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typedef struct {
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uint32_t reg;
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uint32_t pad[3];
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uint32_t data;
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} ioapic_t;
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static const apic_processor_entry_t* apic_processors[MAX_CORES] = {[0 ... MAX_CORES-1] = NULL};
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static uint32_t boot_processor = MAX_CORES;
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static apic_mp_t* apic_mp = NULL;
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static apic_config_table_t* apic_config = NULL;
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static uint32_t lapic = 0;
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static volatile ioapic_t* ioapic = NULL;
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static uint32_t icr = 0;
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static uint32_t ncores = 1;
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static uint8_t irq_redirect[16] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0xA, 0xB, 0xC, 0xD, 0xE, 0xF};
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#if MAX_CORES > 1
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static uint8_t boot_code[] = { 0xFA, 0x0F, 0x01, 0x16, 0x3B, 0x70, 0x0F, 0x20, 0xC0, 0x0C, 0x01, 0x0F, 0x22, 0xC0, 0x66, 0xEA, 0x16, 0x70, 0x00, 0x00, 0x08, 0x00, 0x31, 0xC0, 0x66, 0xB8, 0x10, 0x00, 0x8E, 0xD8, 0x8E, 0xC0, 0x8E, 0xE0, 0x8E, 0xE8, 0x8E, 0xD0, 0xBC, 0xEF, 0xBE, 0xAD, 0xDE, 0x68, 0xAD, 0xDE, 0xAD, 0xDE, 0x6A, 0x00, 0xEA, 0xDE, 0xC0, 0xAD, 0xDE, 0x08, 0x00, 0xEB, 0xFE, 0x17, 0x00, 0x41, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x9A, 0xCF, 0x00, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x92, 0xCF, 0x00};
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static atomic_int32_t cpu_online = ATOMIC_INIT(1);
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#endif
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static uint8_t initialized = 0;
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spinlock_t bootlock = SPINLOCK_INIT;
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// forward declaration
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static int lapic_reset(void);
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static inline uint32_t lapic_read(uint32_t addr)
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{
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return *((volatile uint32_t*) (lapic+addr));
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}
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static inline void lapic_write(uint32_t addr, uint32_t value)
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{
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/*
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* to avoid a pentium bug, we have to read a apic register
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* before we write a value to this register
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*/
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asm volatile ("movl (%%eax), %%edx; movl %%ebx, (%%eax)" :: "a"(lapic+addr), "b"(value) : "%edx");
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//*((volatile uint32_t*) (lapic+addr)) = value;
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}
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static inline uint32_t ioapic_read(uint32_t reg)
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{
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ioapic->reg = reg;
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return ioapic->data;
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}
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static inline void ioapic_write(uint32_t reg, uint32_t value)
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{
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ioapic->reg = reg;
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ioapic->data = value;
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}
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/*
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* Send a 'End of Interrupt' command to the APIC
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*/
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void apic_eoi(void)
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{
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if (BUILTIN_EXPECT(lapic, 1))
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lapic_write(APIC_EOI, 0);
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}
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uint32_t apic_cpu_id(void)
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{
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if (lapic && initialized)
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return ((lapic_read(APIC_ID)) >> 24);
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return 0;
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}
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static inline void apic_set_cpu_id(uint32_t id)
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{
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if (lapic && initialized)
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lapic_write(APIC_ID, id << 24);
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}
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static inline uint32_t apic_version(void)
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{
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if (lapic)
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return lapic_read(APIC_VERSION) & 0xFF;
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return 0;
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}
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static inline uint32_t apic_lvt_entries(void)
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{
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if (lapic)
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return (lapic_read(APIC_VERSION) >> 16) & 0xFF;
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return 0;
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}
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int has_apic(void)
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{
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return (lapic != 0);
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}
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int apic_is_enabled(void)
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{
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return (lapic && initialized);
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}
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#if MAX_CORES > 1
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static inline void set_ipi_dest(uint32_t cpu_id) {
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uint32_t tmp;
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tmp = lapic_read(APIC_ICR2);
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tmp &= 0x00FFFFFF;
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tmp |= (cpu_id << 24);
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lapic_write(APIC_ICR2, tmp);
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}
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int ipi_tlb_flush(void)
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{
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uint32_t flags;
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uint32_t i, j;
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if (atomic_int32_read(&cpu_online) == 1)
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return 0;
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if (lapic_read(APIC_ICR1) & APIC_ICR_BUSY) {
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kputs("ERROR: previous send not complete");
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return -EIO;
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}
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flags = irq_nested_disable();
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if (atomic_int32_read(&cpu_online) == ncores) {
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lapic_write(APIC_ICR1, APIC_INT_ASSERT|APIC_DEST_ALLBUT|APIC_DM_FIXED|124);
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j = 0;
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while((lapic_read(APIC_ICR1) & APIC_ICR_BUSY) && (j < 1000))
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j++; // wait for it to finish, give up eventualy tho
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} else {
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for(i=0; i<atomic_int32_read(&cpu_online); i++)
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{
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if (i == smp_id())
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continue;
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set_ipi_dest(i);
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lapic_write(APIC_ICR1, APIC_INT_ASSERT|APIC_DM_FIXED|124);
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j = 0;
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while((lapic_read(APIC_ICR1) & APIC_ICR_BUSY) && (j < 1000))
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j++; // wait for it to finish, give up eventualy tho
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}
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}
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irq_nested_enable(flags);
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return 0;
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}
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#if 0
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static int apic_send_ipi(uint32_t id, uint32_t mode, uint32_t vector)
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{
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uint32_t i = 0;
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if(lapic_read(APIC_ICR1) & APIC_ICR_BUSY) {
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kprintf("ERROR: previous send not complete");
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return -EIO;
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}
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/* set destination and data */
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lapic_write(APIC_ICR2, (id << 24));
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lapic_write(APIC_ICR1, APIC_INT_ASSERT|mode|vector);
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while((lapic_read(APIC_ICR1) & APIC_ICR_BUSY) && (i < 1000))
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i++; // wait for it to finish, give up eventualy tho
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return ((lapic_read(APIC_ICR1) & APIC_ICR_BUSY) ? -EIO : 0); // did it fail (still delivering) or succeed ?
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}
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#endif
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/*
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* use the universal startup algorithm of Intel's MultiProcessor Specification
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*/
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static int wakeup_ap(uint32_t start_eip, uint32_t id)
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{
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static char* reset_vector = 0;
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uint32_t i;
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kprintf("Wakeup application processor %d via IPI\n", id);
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// set shutdown code to 0x0A
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cmos_write(0x0F, 0x0A);
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if (!reset_vector) {
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reset_vector = (char*) map_region(0x00, 0x00, 1, MAP_KERNEL_SPACE|MAP_NO_CACHE);
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reset_vector += 0x467; // add base address of the reset vector
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kprintf("Map reset vector to %p\n", reset_vector);
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}
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*((volatile unsigned short *) (reset_vector+2)) = start_eip >> 4;
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*((volatile unsigned short *) reset_vector) = 0x00;
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if (lapic_read(APIC_ICR1) & APIC_ICR_BUSY) {
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kputs("ERROR: previous send not complete");
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return -EIO;
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}
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//kputs("Send IPI\n");
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// send out INIT to AP
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set_ipi_dest(id);
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lapic_write(APIC_ICR1, APIC_INT_LEVELTRIG|APIC_INT_ASSERT|APIC_DM_INIT);
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udelay(200);
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// reset INIT
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lapic_write(APIC_ICR1, APIC_INT_LEVELTRIG|APIC_DM_INIT);
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udelay(10000);
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// send out the startup
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set_ipi_dest(id);
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lapic_write(APIC_ICR1, APIC_DM_STARTUP|(start_eip >> 12));
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udelay(200);
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// do it again
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set_ipi_dest(id);
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lapic_write(APIC_ICR1, APIC_DM_STARTUP|(start_eip >> 12));
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udelay(200);
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//kputs("IPI done...\n");
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i = 0;
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while((lapic_read(APIC_ICR1) & APIC_ICR_BUSY) && (i < 1000))
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i++; // wait for it to finish, give up eventualy tho
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return ((lapic_read(APIC_ICR1) & APIC_ICR_BUSY) ? -EIO : 0); // did it fail (still delivering) or succeed ?
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}
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/*
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* This is defined in entry.asm. We use this to properly reload
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* the new segment registers
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*/
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extern void gdt_flush(void);
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/*
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* This is defined in entry.asm and initialized the processors.
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*/
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extern void cpu_init(void);
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/*
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* platform independent entry point of the application processors
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*/
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extern int smp_main(void);
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void smp_start(uint32_t id)
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{
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uint32_t i;
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atomic_int32_inc(&cpu_online);
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// reset APIC and set id
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lapic_reset();
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apic_set_cpu_id(id);
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kprintf("Application processor %d is entering its idle task\n", apic_cpu_id());
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// initialize default cpu features
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cpu_init();
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// use the same gdt like the boot processors
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gdt_flush();
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// install IDT
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idt_install();
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// enable additional cpu features
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cpu_detection();
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/* enable paging */
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write_cr3((uint32_t)get_boot_pgd());
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i = read_cr0();
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i = i | (1 << 31);
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write_cr0(i);
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// reset APIC and set id
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lapic_reset(); // sets also the timer interrupt
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apic_set_cpu_id(id);
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/*
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* we turned on paging
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* => now, we are able to register our task for Task State Switching
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*/
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register_task(per_core(current_task));
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smp_main();
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// idle loop
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while(1) ;
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}
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#endif
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static unsigned int* search_apic(unsigned int base, unsigned int limit) {
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uint32_t* ptr;
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for (ptr = (uint32_t*) base; (uint32_t) ptr < limit; ptr++) {
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if (*ptr == MP_FLT_SIGNATURE) {
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if (!(((apic_mp_t*)ptr)->version > 4) && ((apic_mp_t*)ptr)->features[0])
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return ptr;
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}
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}
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return NULL;
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}
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#if MAX_CORES > 1
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int smp_init(void)
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{
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uint32_t i, j;
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char* bootaddr;
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int err;
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if (ncores <= 1)
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return -EINVAL;
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for(i=1; (i<ncores) && (i<MAX_CORES); i++)
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{
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/*
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* dirty hack: Copy 16bit startup code (see tools/smp_setup.asm)
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* to a 16bit address. Wakeup the other cores via IPI. They start
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* at this address in real mode, switch to protected and finally
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* they jump to smp_main.
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*
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* The page at SMP_SETUP_ADDR is already reserved for this hack!
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*/
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bootaddr = (char*) SMP_SETUP_ADDR;
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memcpy(bootaddr, boot_code, sizeof(boot_code));
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for(j=0; j<sizeof(boot_code)-sizeof(uint32_t); j++)
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{
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// replace 0xDEADC0DE with the address of the smp entry code
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if (*((uint32_t*) (bootaddr+j)) == 0xDEADC0DE) {
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*((uint32_t*) (bootaddr+j)) = (size_t) smp_start;
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kprintf("Set entry point of the application processors at 0x%x\n", (size_t) smp_start);
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}
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// replace APIC ID 0xDEADDEAD
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if (*((uint32_t*) (bootaddr+j)) == 0xDEADDEAD)
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*((uint32_t*) (bootaddr+j)) = i;
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// replace 0xDEADBEEF with the addres of the stack
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if (*((uint32_t*) (bootaddr+j)) == 0xDEADBEEF) {
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size_t esp = get_idle_task(i);
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*((uint32_t*) (bootaddr+j)) = (uint32_t) esp;
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if ((int) esp < 0)
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kprintf("Invalid stack value\n");
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kprintf("Set stack of the application processors to 0x%x\n", esp);
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}
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}
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//kprintf("size of the boot_code %d\n", sizeof(boot_code));
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err = wakeup_ap((uint32_t)bootaddr, i);
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if (err)
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kprintf("Unable to wakeup application processor %d: %d\n", i, err);
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j = 0;
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while((ncores != atomic_int32_read(&cpu_online)) && (j < 100)) {
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udelay(1000);
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j++;
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}
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}
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kprintf("%d cores online\n", atomic_int32_read(&cpu_online));
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return 0;
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}
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#endif
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static int lapic_reset(void)
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{
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uint32_t max_lvt;
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if (!lapic)
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return -ENXIO;
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max_lvt = apic_lvt_entries();
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lapic_write(APIC_SVR, 0x17F); // enable the apic and connect to the idt entry 127
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lapic_write(APIC_TPR, 0x00); // allow all interrupts
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if (icr) {
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lapic_write(APIC_DCR, 0xB); // set it to 1 clock increments
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lapic_write(APIC_LVT_T, 0x2007B); // connects the timer to 123 and enables it
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lapic_write(APIC_ICR, icr);
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} else
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lapic_write(APIC_LVT_T, 0x10000); // disable timer interrupt
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if (max_lvt >= 4)
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lapic_write(APIC_LVT_TSR, 0x10000); // disable thermal sensor interrupt
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if (max_lvt >= 5)
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lapic_write(APIC_LVT_PMC, 0x10000); // disable performance counter interrupt
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lapic_write(APIC_LINT0, 0x7C); // connect LINT0 to idt entry 124
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lapic_write(APIC_LINT1, 0x7D); // connect LINT1 to idt entry 125
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lapic_write(APIC_LVT_ER, 0x7E); // connect error to idt entry 126
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return 0;
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}
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int map_apic(void)
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{
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uint32_t i;
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if (!has_apic())
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return -ENXIO;
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lapic = map_region(0 /*lapic*/, lapic, 1, MAP_KERNEL_SPACE|MAP_NO_CACHE);
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if (BUILTIN_EXPECT(!lapic, 0))
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return -ENXIO;
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kprintf("Mapped LAPIC at 0x%x\n", lapic);
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if (ioapic) {
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size_t old = 0;
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ioapic = (ioapic_t*) map_region(0 /*(size_t)ioapic*/, (size_t) ioapic, 1, MAP_KERNEL_SPACE|MAP_NO_CACHE);
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kprintf("Mapped IOAPIC at 0x%x\n", ioapic);
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// map all processor entries
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for(i=0; i<MAX_CORES; i++) {
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if (apic_processors[i] && (old != (((size_t)apic_processors[i]) & 0xFFFFF000)))
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old = map_region(((size_t) apic_processors[i]) & 0xFFFFF000, ((size_t) apic_processors[i]) & 0xFFFFF000, 1, MAP_KERNEL_SPACE|MAP_NO_CACHE);
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}
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}
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return 0;
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}
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/*
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* detects the timer frequency of the APIC and restart
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* the APIC timer with the correct period
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*/
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int apic_calibration(void)
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{
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uint32_t i;
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uint32_t flags;
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#ifndef CONFIG_ROCKCREEK
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uint64_t ticks, old;
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uint32_t diff;
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#else
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uint64_t start, end, ticks;
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uint32_t diff;
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#endif
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if (!has_apic())
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return -ENXIO;
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#ifndef CONFIG_ROCKCREEK
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old = get_clock_tick();
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/* wait for the next time slice */
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while((ticks = get_clock_tick()) - old == 0)
|
|
HALT;
|
|
|
|
flags = irq_nested_disable();
|
|
lapic_write(APIC_DCR, 0xB); // set it to 1 clock increments
|
|
lapic_write(APIC_LVT_T, 0x2007B); // connects the timer to 123 and enables it
|
|
lapic_write(APIC_ICR, 0xFFFFFFFFUL);
|
|
irq_nested_enable(flags);
|
|
|
|
/* wait 3 time slices to determine a ICR */
|
|
while(get_clock_tick() - ticks < 3)
|
|
HALT;
|
|
|
|
diff = 0xFFFFFFFFUL - lapic_read(APIC_CCR);
|
|
icr = diff / 3;
|
|
|
|
flags = irq_nested_disable();
|
|
lapic_reset();
|
|
irq_nested_enable(flags);
|
|
|
|
// Now, MetalSVM is able to use the APIC => Therefore, we disable the PIC
|
|
outportb(0xA1, 0xFF);
|
|
outportb(0x21, 0xFF);
|
|
#else
|
|
/*
|
|
* On the SCC, we already know the processor frequency
|
|
* and possess no PIC timer. Therfore, we use the rdtsc to
|
|
* to calibrate the APIC timer.
|
|
*/
|
|
flags = irq_nested_disable();
|
|
|
|
lapic_write(APIC_DCR, 0xB); // set it to 1 clock increments
|
|
lapic_write(APIC_LVT_T, 0x2007B); // connects the timer to 123 and enables it
|
|
lapic_write(APIC_ICR, 0xFFFFFFFFUL);
|
|
|
|
/* wait 3 time slices to determine a ICR */
|
|
mb();
|
|
start = rdtsc();
|
|
do {
|
|
mb();
|
|
end = rdtsc();
|
|
ticks = end > start ? end - start : start - end;
|
|
} while(ticks*TIMER_FREQ < 3*RC_REFCLOCKMHZ*1000000UL);
|
|
|
|
diff = 0xFFFFFFFFUL - lapic_read(APIC_CCR);
|
|
icr = diff / 3;
|
|
|
|
lapic_reset();
|
|
|
|
irq_nested_enable(flags);
|
|
#endif
|
|
|
|
kprintf("APIC calibration determines an ICR of 0x%x\n", icr);
|
|
|
|
flags = irq_nested_disable();
|
|
|
|
if (ioapic) {
|
|
// now, we don't longer need the IOAPIC timer and turn it off
|
|
ioapic_intoff(0, apic_processors[boot_processor]->id);
|
|
// now lets turn everything else on
|
|
for(i=1; i<24; i++)
|
|
ioapic_inton(i, apic_processors[boot_processor]->id);
|
|
}
|
|
initialized = 1;
|
|
#if MAX_CORES > 1
|
|
smp_init();
|
|
#endif
|
|
irq_nested_enable(flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int apic_probe(void)
|
|
{
|
|
size_t addr;
|
|
uint32_t i, count;
|
|
int isa_bus = -1;
|
|
|
|
apic_mp = (apic_mp_t*) search_apic(0xF0000, 0x100000);
|
|
if (apic_mp)
|
|
goto found_mp;
|
|
apic_mp = (apic_mp_t*) search_apic(0x9F000, 0xA0000);
|
|
if (apic_mp)
|
|
goto found_mp;
|
|
|
|
// searching MP signature in the reserved memory areas
|
|
#ifdef CONFIG_MULTIBOOT
|
|
if (mb_info && (mb_info->flags & MULTIBOOT_INFO_MEM_MAP)) {
|
|
multiboot_memory_map_t* mmap = (multiboot_memory_map_t*) mb_info->mmap_addr;
|
|
multiboot_memory_map_t* mmap_end = (void*) ((size_t) mb_info->mmap_addr + mb_info->mmap_length);
|
|
|
|
while (mmap < mmap_end) {
|
|
if (mmap->type == MULTIBOOT_MEMORY_RESERVED) {
|
|
addr = mmap->addr;
|
|
|
|
for(i=0; i<mmap->len-sizeof(uint32_t); i++, addr++) {
|
|
if (*((uint32_t*) addr) == MP_FLT_SIGNATURE) {
|
|
apic_mp = (apic_mp_t*) addr;
|
|
if (!(apic_mp->version > 4) && apic_mp->features[0])
|
|
goto found_mp;
|
|
}
|
|
}
|
|
|
|
}
|
|
mmap++;
|
|
}
|
|
}
|
|
#endif
|
|
found_mp:
|
|
if (!apic_mp)
|
|
goto no_mp;
|
|
|
|
kprintf("System uses Multiprocessing Specification 1.%u\n", apic_mp->version);
|
|
kprintf("MP features 1: %u\n", apic_mp->features[0]);
|
|
|
|
if (apic_mp->features[0]) {
|
|
kputs("Currently, MetalSVM supports only multiprocessing via the MP config tables!\n");
|
|
goto no_mp;
|
|
}
|
|
|
|
apic_config = (apic_config_table_t*) apic_mp->mp_config;
|
|
if (!apic_config || strncmp((void*) &apic_config->signature, "PCMP", 4) !=0) {
|
|
kputs("Invalid MP config table\n");
|
|
goto no_mp;
|
|
}
|
|
|
|
addr = (size_t) apic_config;
|
|
addr += sizeof(apic_config_table_t);
|
|
if (addr % 4)
|
|
addr += 4 - addr % 4;
|
|
|
|
// search the ISA bus => required to redirect the IRQs
|
|
for(i=0; i<apic_config->entry_count; i++) {
|
|
switch(*((uint8_t*) addr)) {
|
|
case 0:
|
|
addr += 20;
|
|
break;
|
|
case 1: {
|
|
apic_bus_entry_t* mp_bus;
|
|
|
|
mp_bus = (apic_bus_entry_t*) addr;
|
|
if (mp_bus->name[0] == 'I' && mp_bus->name[1] == 'S' &&
|
|
mp_bus->name[2] == 'A')
|
|
isa_bus = i;
|
|
}
|
|
default:
|
|
addr += 8;
|
|
}
|
|
}
|
|
|
|
addr = (size_t) apic_config;
|
|
addr += sizeof(apic_config_table_t);
|
|
if (addr % 4)
|
|
addr += 4 - addr % 4;
|
|
|
|
for(i=0, count=0; i<apic_config->entry_count; i++) {
|
|
if (*((uint8_t*) addr) == 0) { // cpu entry
|
|
if (i < MAX_CORES) {
|
|
apic_processors[i] = (apic_processor_entry_t*) addr;
|
|
if (!(apic_processors[i]->cpu_flags & 0x01)) // is the processor usable?
|
|
apic_processors[i] = NULL;
|
|
else if (apic_processors[i]->cpu_flags & 0x02)
|
|
boot_processor = i;
|
|
}
|
|
count++;
|
|
addr += 20;
|
|
} else if (*((uint8_t*) addr) == 2) { // IO_APIC
|
|
apic_io_entry_t* io_entry = (apic_io_entry_t*) addr;
|
|
ioapic = (ioapic_t*) io_entry->addr;
|
|
addr += 8;
|
|
kprintf("Found IOAPIC at 0x%x (ver. 0x%x)\n", ioapic,
|
|
ioapic_read(IOAPIC_REG_VER));
|
|
} else if (*((uint8_t*) addr) == 3) { // IO_INT
|
|
apic_ioirq_entry_t* extint = (apic_ioirq_entry_t*) addr;
|
|
if (extint->src_bus == isa_bus) {
|
|
irq_redirect[extint->src_irq] = extint->dest_intin;
|
|
kprintf("Redirect irq %u -> %u\n", extint->src_irq, extint->dest_intin);
|
|
}
|
|
addr += 8;
|
|
} else addr += 8;
|
|
}
|
|
kprintf("Found %u cores\n", count);
|
|
|
|
if (count > MAX_CORES) {
|
|
kputs("Found too many cores! Increase the macro MAX_CORES!\n");
|
|
goto no_mp;
|
|
}
|
|
ncores = count;
|
|
|
|
check_lapic:
|
|
if (apic_config) {
|
|
lapic = apic_config->lapic;
|
|
} else {
|
|
uint32_t edx, dummy;
|
|
|
|
cpuid(0x1, &dummy, &dummy, &dummy, &edx);
|
|
if (edx & (1 << 9))
|
|
lapic = 0xFEE00000;
|
|
}
|
|
|
|
if (!lapic)
|
|
goto out;
|
|
|
|
kprintf("Found APIC at 0x%x\n", lapic);
|
|
kprintf("Maximum LVT Entry: 0x%x\n", apic_lvt_entries());
|
|
kprintf("APIC Version: 0x%x\n", apic_version());
|
|
|
|
if (!((apic_version() >> 4))) {
|
|
kprintf("Currently, MetalSVM didn't supports extern APICs!\n");
|
|
goto out;
|
|
}
|
|
|
|
if (apic_lvt_entries() < 3) {
|
|
kprintf("LVT is too small\n");
|
|
goto out;
|
|
}
|
|
|
|
return 0;
|
|
|
|
out:
|
|
apic_mp = NULL;
|
|
apic_config = NULL;
|
|
lapic = 0;
|
|
ncores = 1;
|
|
return -ENXIO;
|
|
|
|
no_mp:
|
|
apic_mp = NULL;
|
|
apic_config = NULL;
|
|
ncores = 1;
|
|
goto check_lapic;
|
|
}
|
|
|
|
#if MAX_CORES > 1
|
|
static void apic_tlb_handler(struct state *s)
|
|
{
|
|
uint32_t val = read_cr3();
|
|
|
|
if (val)
|
|
write_cr3(val);
|
|
}
|
|
#endif
|
|
|
|
static void apic_err_handler(struct state *s)
|
|
{
|
|
kprintf("Got APIC error 0x%x\n", lapic_read(APIC_ESR));
|
|
}
|
|
|
|
int apic_init(void)
|
|
{
|
|
int ret;
|
|
|
|
ret = apic_probe();
|
|
if (ret)
|
|
return ret;
|
|
|
|
// set APIC error handler
|
|
irq_install_handler(126, apic_err_handler);
|
|
#if MAX_CORES > 1
|
|
irq_install_handler(124, apic_tlb_handler);
|
|
#endif
|
|
|
|
#if 0
|
|
// initialize local apic
|
|
ret = lapic_reset();
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (ioapic) {
|
|
uint32_t i;
|
|
|
|
// enable timer interrupt
|
|
ioapic_inton(0, apic_processors[boot_processor]->id);
|
|
// now lets turn everything else off
|
|
for(i=1; i<24; i++)
|
|
ioapic_intoff(i, apic_processors[boot_processor]->id);
|
|
}
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
int ioapic_inton(uint8_t irq, uint8_t apicid)
|
|
{
|
|
ioapic_route_t route;
|
|
uint32_t off;
|
|
|
|
if (BUILTIN_EXPECT(irq > 24, 0)){
|
|
kprintf("IOAPIC: trying to turn on irq %i which is too high\n", irq);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (irq < 16)
|
|
off = irq_redirect[irq]*2;
|
|
else
|
|
off = irq*2;
|
|
#if 0
|
|
route.lower.whole = ioapic_read(IOAPIC_REG_TABLE+1+off);
|
|
route.dest.upper = ioapic_read(IOAPIC_REG_TABLE+off);
|
|
route.lower.bitfield.mask = 0; // turn it on (stop masking)
|
|
#else
|
|
route.lower.bitfield.dest_mode = 0;
|
|
route.lower.bitfield.mask = 0;
|
|
route.dest.physical.physical_dest = apicid; // send to the boot processor
|
|
route.lower.bitfield.delivery_mode = 0;
|
|
route.lower.bitfield.polarity = 0;
|
|
route.lower.bitfield.trigger = 0;
|
|
route.lower.bitfield.vector = 0x20+irq;
|
|
route.lower.bitfield.mask = 0; // turn it on (stop masking)
|
|
#endif
|
|
|
|
ioapic_write(IOAPIC_REG_TABLE+off, route.lower.whole);
|
|
ioapic_write(IOAPIC_REG_TABLE+1+off, route.dest.upper);
|
|
|
|
route.dest.upper = ioapic_read(IOAPIC_REG_TABLE+1+off);
|
|
route.lower.whole = ioapic_read(IOAPIC_REG_TABLE+off);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int ioapic_intoff(uint8_t irq, uint8_t apicid)
|
|
{
|
|
ioapic_route_t route;
|
|
uint32_t off;
|
|
|
|
if (BUILTIN_EXPECT(irq > 24, 0)){
|
|
kprintf("IOAPIC: trying to turn on irq %i which is too high\n", irq);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (irq < 16)
|
|
off = irq_redirect[irq]*2;
|
|
else
|
|
off = irq*2;
|
|
|
|
#if 0
|
|
route.lower.whole = ioapic_read(IOAPIC_REG_TABLE+1+off);
|
|
route.dest.upper = ioapic_read(IOAPIC_REG_TABLE+off);
|
|
route.lower.bitfield.mask = 1; // turn it off (start masking)
|
|
#else
|
|
route.lower.bitfield.dest_mode = 0;
|
|
route.lower.bitfield.mask = 0;
|
|
route.dest.physical.physical_dest = apicid;
|
|
route.lower.bitfield.delivery_mode = 0;
|
|
route.lower.bitfield.polarity = 0;
|
|
route.lower.bitfield.trigger = 0;
|
|
route.lower.bitfield.vector = 0x20+irq;
|
|
route.lower.bitfield.mask = 1; // turn it off (start masking)
|
|
#endif
|
|
|
|
ioapic_write(IOAPIC_REG_TABLE+off, route.lower.whole);
|
|
ioapic_write(IOAPIC_REG_TABLE+1+off, route.dest.upper);
|
|
|
|
return 0;
|
|
}
|