0419142d83
- works only on the SCC git-svn-id: http://svn.lfbs.rwth-aachen.de/svn/scc/trunk/MetalSVM@269 315a16e6-25f9-4109-90ae-ca3045a26c18
127 lines
3 KiB
C
127 lines
3 KiB
C
/*
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* Copyright 2010 Stefan Lankes, Chair for Operating Systems,
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* RWTH Aachen University
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* This file is part of MetalSVM.
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*/
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#ifndef __ARCH_PROCESSOR_H__
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#define __ARCH_PROCESSOR_H__
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#include <metalsvm/stddef.h>
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#include <asm/gdt.h>
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#include <asm/apic.h>
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#ifdef CONFIG_PCI
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#include <asm/pci.h>
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#endif
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#ifdef CONFIG_ROCKCREEK
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#include <asm/scc.h>
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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inline static uint64_t rdtsc(void)
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{
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uint64_t x;
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asm volatile ("rdtsc" : "=A" (x));
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return x;
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}
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inline static void flush_cache(void) {
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asm volatile ("wbinvd" : : : "memory");
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}
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inline static void invalid_cache(void) {
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asm volatile ("invd");
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}
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inline static int get_return_value(void) {
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int ret;
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asm volatile ("movl %%eax, %0" : "=r"(ret));
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return ret;
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}
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/* Force strict CPU ordering */
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#ifdef CONFIG_ROCKCREEK
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inline static void mb(void) { asm volatile ("lock; addl $0,0(%%esp)" ::: "memory"); }
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inline static void rmb(void) { asm volatile ("lock; addl $0,0(%%esp)" ::: "memory"); }
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inline static void wmb(void) { asm volatile ("lock; addl $0,0(%%esp)" ::: "memory"); }
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#else
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inline static void mb(void) { asm volatile("mfence" ::: "memory"); }
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inline static void rmb(void) { asm volatile("lfence" ::: "memory"); }
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inline static void wmb(void) { asm volatile("sfence" ::: "memory"); }
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#endif
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inline static void cpuid(uint32_t code, uint32_t* a, uint32_t* b, uint32_t* c, uint32_t* d) {
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asm volatile ("cpuid" : "=a"(*a), "=b"(*b), "=c"(*c), "=d"(*d) : "0"(code));
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}
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inline static void flush_pipeline(void) {
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uint32_t low = 0;
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uint32_t high = 0;
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uint32_t code = 0;
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asm volatile ("cpuid" : "=a"(low), "=d"(high) : "0"(code) : "%ebx", "%ecx");
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}
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inline static uint64_t rdmsr(uint32_t msr) {
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uint32_t low, high;
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asm volatile ("rdmsr" : "=a" (low), "=d" (high) : "c" (msr));
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return ((uint64_t)high << 32) | low;
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}
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/*
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* invalidate (not flush!) lines in L1 that map to MPB lines
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*/
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inline static void cache_invalidate(void) {
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#ifdef CONFIG_ROCKCREEK
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asm volatile (".byte 0x0f; .byte 0x0a;\n" ); // CL1FLUSHMB
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#endif
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}
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#define NOP1 asm volatile ("nop")
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#define NOP2 asm volatile ("nop;nop")
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#define NOP4 asm volatile ("nop;nop;nop;nop")
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#define NOP8 asm volatile ("nop;nop;nop;nop;nop;nop;nop;nop")
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inline static int system_init(void)
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{
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#ifdef CONFIG_ROCKCREEK
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scc_init();
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#endif
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gdt_install();
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apic_init();
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#ifdef CONFIG_PCI
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pci_init();
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#endif
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return 0;
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}
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inline static int system_calibration(void)
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{
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apic_calibration();
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return 0;
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}
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#ifdef __cplusplus
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}
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#endif
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#endif
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