227cc19890
New features: - support of kernel tasks in 64bit mode - support of LwIP in 64bit mode Missing features in 64bit mode - user-level support - APIC support => SMP support To create a 64bit version of the MetalSVM kernel, the compiler flags “-m64 -mno-red-zone” and the assembler flags “-felf64” has to be used. Please use qemu-system-x86_64 as test platform. Notice, metalsvm.elf is a 32bit ELF file. However, it contains (beside the startup code) only 64bit code. This is required because GRUB doesn’t boot 64bit ELF kernels. Therefore, for disassembling via objdump the flag “-M x86-64” has to be used.
387 lines
9 KiB
C
387 lines
9 KiB
C
/*
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* Copyright 2010 Stefan Lankes, Chair for Operating Systems,
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* RWTH Aachen University
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* This file is part of MetalSVM.
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*/
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/**
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* @author Stefan Lankes
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* @file arch/x86/include/asm/processor.h
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* @brief CPU-specific functions
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*
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* This file contains structures and functions related to CPU-specific assembler commands.
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*/
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#ifndef __ARCH_PROCESSOR_H__
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#define __ARCH_PROCESSOR_H__
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#include <metalsvm/stddef.h>
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#include <asm/gdt.h>
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#include <asm/apic.h>
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#ifdef CONFIG_PCI
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#include <asm/pci.h>
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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// feature list 1
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#define CPU_FEATURE_FPU (1 << 0)
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#define CPU_FEATURE_MMX (1 << 23)
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#define CPU_FEATURE_FXSR (1 << 24)
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#define CPU_FEATURE_SSE (1 << 25)
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#define CPU_FEATURE_SSE2 (1 << 26)
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// feature list 2
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#define CPU_FEATURE_AVX (1 << 28)
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typedef struct {
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uint32_t feature1, feature2;
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} cpu_info_t;
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extern cpu_info_t cpu_info;
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// determine the cpu features
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int cpu_detection(void);
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inline static uint32_t has_fpu(void)
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{
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return (cpu_info.feature1 & CPU_FEATURE_FPU);
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}
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inline static uint32_t has_fxsr(void)
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{
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return (cpu_info.feature1 & CPU_FEATURE_FXSR);
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}
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inline static uint32_t has_xmm(void)
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{
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return (cpu_info.feature1 & CPU_FEATURE_SSE);
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}
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inline static uint32_t has_avx(void)
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{
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return (cpu_info.feature2 & CPU_FEATURE_AVX);
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}
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/** @brief Read out time stamp counter
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*
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* The rdtsc asm command puts a 64 bit time stamp value
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* into EDX:EAX.
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*
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* @return The 64 bit time stamp value
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*/
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inline static uint64_t rdtsc(void)
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{
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uint64_t x;
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asm volatile ("rdtsc" : "=A" (x));
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return x;
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}
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/** @brief Flush cache
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*
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* The wbinvd asm instruction which stands for "Write back and invalidate"
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* is used here
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*/
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inline static void flush_cache(void) {
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asm volatile ("wbinvd" ::: "memory");
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}
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/** @brief Invalidate cache
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*
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* The invd asm instruction which invalidates cache without writing back
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* is used here
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*/
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inline static void invalidate_cache(void) {
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asm volatile ("invd" ::: "memory");
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}
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/** @brief Get return value from EAX
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*
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* If there is some return value in eax, this is the C-way to get it into a var
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* if the function did not return it the normal way.
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*
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* @return The return value which wasn't returned as usual.
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*/
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inline static int get_return_value(void) {
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int ret;
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asm volatile ("movl %%eax, %0" : "=r"(ret));
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return ret;
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}
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/* Force strict CPU ordering */
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#ifdef CONFIG_ROCKCREEK
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inline static void mb(void) { asm volatile ("lock; addl $0,0(%%esp)" ::: "memory", "cc"); }
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inline static void rmb(void) { asm volatile ("lock; addl $0,0(%%esp)" ::: "memory", "cc"); }
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inline static void wmb(void) { asm volatile ("lock; addl $0,0(%%esp)" ::: "memory", "cc"); }
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#else
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inline static void mb(void) { asm volatile("mfence" ::: "memory"); }
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inline static void rmb(void) { asm volatile("lfence" ::: "memory"); }
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inline static void wmb(void) { asm volatile("sfence" ::: "memory"); }
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#endif
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/** @brief Read out CPU ID
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*
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* The cpuid asm-instruction does fill some information into registers and
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* this function fills those register values into the given uint32_t vars.\n
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* \n
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* Some people are used to flush the pipeline with this instruction;
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* There is another function for doing this in MetalSVM called flush_pipeline().
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* It basically does the same. Just use it if you only want to flush the pipeline
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* as it will be more comfortable because it does not take any parameters.
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*
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* @param code Input parameter for the cpuid instruction. Take a look into the intel manual.
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* @param a EAX value will be stores here
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* @param b EBX value will be stores here
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* @param c ECX value will be stores here
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* @param d EDX value will be stores here
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*/
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inline static void cpuid(uint32_t code, uint32_t* a, uint32_t* b, uint32_t* c, uint32_t* d) {
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asm volatile ("cpuid" : "=a"(*a), "=b"(*b), "=c"(*c), "=d"(*d) : "0"(code));
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}
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/** @brief Read MSR
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*
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* The asm instruction rdmsr which stands for "Read from model specific register"
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* is used here.
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*
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* @param msr The parameter which rdmsr assumes in ECX
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* @return The value rdmsr put into EDX:EAX
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*/
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inline static uint64_t rdmsr(uint32_t msr) {
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uint32_t low, high;
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asm volatile ("rdmsr" : "=a" (low), "=d" (high) : "c" (msr));
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return ((uint64_t)high << 32) | low;
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}
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/** @brief Read cr0 register
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* @return cr0's value
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*/
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static inline size_t read_cr0(void) {
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size_t val;
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asm volatile("mov %%cr0, %0" : "=r"(val));
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return val;
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}
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/** @brief Write a value into cr0 register
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* @param val The value you want to write into cr0
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*/
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static inline void write_cr0(size_t val) {
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asm volatile("mov %0, %%cr0" : : "r"(val));
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}
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/** @brief Read cr2 register
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* @return cr2's value
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*/
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static inline size_t read_cr2(void) {
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size_t val;
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asm volatile("mov %%cr2, %0" : "=r"(val));
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return val;
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}
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/** @brief Read cr3 register
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* @return cr3's value
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*/
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static inline size_t read_cr3(void) {
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size_t val;
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asm volatile("mov %%cr3, %0" : "=r"(val));
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return val;
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}
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/** @brief Write a value into cr3 register
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* @param val The value you want to write into cr3
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*/
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static inline void write_cr3(size_t val) {
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asm volatile("mov %0, %%cr3" : : "r"(val));
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}
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/** @brief Read cr4 register
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* @return cr4's value
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*/
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static inline size_t read_cr4(void) {
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size_t val;
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asm volatile("mov %%cr4, %0" : "=r"(val));
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return val;
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}
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/** @brief Write a value into cr4 register
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* @param val The value you want to write into cr4
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*/
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static inline void write_cr4(size_t val) {
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asm volatile("mov %0, %%cr4" : : "r"(val));
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}
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int ipi_tlb_flush(void);
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/** @brief Flush a specific page entry in TLB
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* @param addr The (virtual) address of the page to flush
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*/
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static inline void tlb_flush_one_page(uint32_t addr)
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{
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asm volatile("invlpg (%0)" : : "r"(addr) : "memory");
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#if MAX_CORES > 1
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/*
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* Currently, we didn't support user-level threads.
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* => User-level applications run only on one
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* and we didn't flush the TLB of the other cores
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*/
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if (addr <= KERNEL_SPACE)
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ipi_tlb_flush();
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#endif
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}
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/** @brief Invalidate the whole TLB
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*
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* Just reads cr3 and writes the same value back into it.
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*/
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static inline void tlb_flush(void)
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{
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uint32_t val = read_cr3();
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if (val)
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write_cr3(val);
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#if MAX_CORES > 1
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ipi_tlb_flush();
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#endif
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}
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/** @brief Read EFLAGS
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*
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* @return The EFLAGS value
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*/
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static inline uint32_t read_eflags(void)
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{
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uint32_t result;
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asm volatile ("pushf; pop %0" : "=r"(result));
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return result;
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}
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/** @brief search the first most significant bit
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*
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* @param i source operand
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* @return
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* - first bit, which is set in the source operand
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* - invalid value, if not bit ist set
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*/
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static inline size_t msb(size_t i)
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{
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size_t ret;
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if (!i)
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return (sizeof(size_t)*8);
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asm volatile ("bsr %1, %0" : "=r"(ret) : "r"(i) : "cc");
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return ret;
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}
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/** @brief search the least significant bit
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*
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* @param i source operand
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* @return
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* - first bit, which is set in the source operand
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* - invalid value, if not bit ist set
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*/
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static inline size_t lsb(size_t i)
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{
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size_t ret;
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if (!i)
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return (sizeof(size_t)*8);
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asm volatile ("bsf %1, %0" : "=r"(ret) : "r"(i) : "cc");
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return ret;
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}
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/** @brief Read extended instruction pointer
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* @return The EIP's value
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*/
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uint32_t read_eip(void);
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/// A one-instruction-do-nothing
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#define NOP1 asm volatile ("nop")
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/// Do nothing for 2 instructions
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#define NOP2 asm volatile ("nop;nop")
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/// Do nothing for 4 instructions
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#define NOP4 asm volatile ("nop;nop;nop;nop")
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/// Do nothing for 8 instructions
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#define NOP8 asm volatile ("nop;nop;nop;nop;nop;nop;nop;nop")
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#define HALT asm volatile ("hlt");
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/** @brief Init several subsystems
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*
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* This function calls the initialization procedures for:
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* - GDT
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* - APIC
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* - PCI [if configured]
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*
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* @return 0 in any case
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*/
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inline static int system_init(void)
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{
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gdt_install();
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#ifdef CONFIG_X86_32
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apic_init();
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#endif
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#ifdef CONFIG_PCI
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pci_init();
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#endif
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cpu_detection();
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return 0;
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}
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/** @brief Detect and read out CPU frequency
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*
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* @return The CPU frequency in MHz
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*/
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uint32_t detect_cpu_frequency(void);
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/** @brief Read out CPU frequency if detected before
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*
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* If you did not issue the detect_cpu_frequency() function before,
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* this function will call it implicitly.
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*
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* @return The CPU frequency in MHz
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*/
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uint32_t get_cpu_frequency(void);
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/** @brief Busywait an microseconds interval of time
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* @param usecs The time to wait in microseconds
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*/
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void udelay(uint32_t usecs);
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/** @brief System calibration
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*
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* This procedure will detect the CPU frequency and calibrate the APIC timer.
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*
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* @return 0 in any case.
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*/
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inline static int system_calibration(void)
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{
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detect_cpu_frequency();
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apic_calibration();
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return 0;
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}
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#ifdef __cplusplus
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}
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#endif
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#endif
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