7294c47c98
- code restructuring - remove some typos in debug messages git-svn-id: http://svn.lfbs.rwth-aachen.de/svn/scc/trunk/MetalSVM@42 315a16e6-25f9-4109-90ae-ca3045a26c18
165 lines
4 KiB
C
165 lines
4 KiB
C
/*
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* Copyright 2010 Stefan Lankes, Chair for Operating Systems,
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* RWTH Aachen University
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* This file is part of MetalSVM.
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*/
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#include <metalsvm/stdio.h>
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#include <metalsvm/string.h>
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#include <asm/irqflags.h>
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#include <asm/io.h>
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#ifdef CONFIG_PCI
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#include <asm/pci.h>
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#include "pcihdr.h"
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/*
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* PCI configuration registers
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*/
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#define PCI_CFID 0x00 /* Configuration ID */
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#define PCI_CFCS 0x04 /* Configurtion Command/Status */
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#define PCI_CFRV 0x08 /* Configuration Revision */
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#define PCI_CFLT 0x0c /* Configuration Latency Timer */
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#define PCI_CBIO 0x10 /* Configuration Base IO Address */
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#define PCI_CBMA 0x14 /* Configuration Base Memory Address */
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#define PCI_CFIT 0x3c /* Configuration Interrupt */
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#define PCI_CFDA 0x40 /* Configuration Driver Area */
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#define PHYS_IO_MEM_START 0
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#define PCI_MEM 0
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#define PCI_INTA 0
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#define PCI_NSLOTS 22
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#define PCI_NBUS 0
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#define PCI_CONF_ADDR_REG 0xcf8
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#define PCI_CONF_FRWD_REG 0xcf8
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#define PCI_CONF_DATA_REG 0xcfc
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#define PCI_IO_CONF_START 0xc000
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#define MAX_BUS 16
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#define MAX_SLOTS 32
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static int mechanism = 0;
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static int initialized = 0;
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static int adapters[MAX_BUS][MAX_SLOTS];
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static void pci_conf_write(int bus, int slot, int off, int val)
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{
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if (mechanism == 1) {
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outportl(PCI_CONF_FRWD_REG, bus);
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outportl(PCI_CONF_ADDR_REG, 0xf0);
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outportl(PCI_IO_CONF_START | (slot << 8) | off, val);
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} else {
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outportl(PCI_CONF_ADDR_REG,
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(0x80000000 | (bus << 16) | (slot << 11) | off));
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outportl(PCI_CONF_DATA_REG, val);
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}
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}
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static int pci_conf_read(int bus, int slot, int off)
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{
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unsigned int data = -1;
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outportl(PCI_CONF_ADDR_REG,
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(0x80000000 | (bus << 16) | (slot << 11) | off));
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data = inportl(PCI_CONF_DATA_REG);
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if ((data == 0xffffffff) && (slot < 0x10)) {
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outportl(PCI_CONF_FRWD_REG, bus);
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outportl(PCI_CONF_ADDR_REG, 0xf0);
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data = inportl(PCI_IO_CONF_START | (slot << 8) | off);
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if (data == 0xffffffff)
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return (data);
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if (!mechanism)
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mechanism = 1;
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} else if (!mechanism)
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mechanism = 2;
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return (data);
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}
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static int pci_what_irq(int bus, int slot, int intx)
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{
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return pci_conf_read(bus, slot, PCI_CFIT) & 0xff;
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}
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static int find_pci_adapters(void)
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{
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int slot, bus;
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if (initialized)
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return 0;
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initialized = 1;
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for (bus = 0; bus < MAX_BUS; bus++)
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for (slot = 0; slot < MAX_SLOTS; slot++)
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adapters[bus][slot] = pci_conf_read(bus, slot, PCI_CFID);
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return 0;
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}
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int pci_init(void)
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{
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memset(adapters, -1, MAX_BUS*MAX_SLOTS*sizeof(int));
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return find_pci_adapters();
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}
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int print_pci_adapters(void)
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{
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int slot, bus;
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int i, counter = 0;
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if (!initialized)
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return -1;
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for (bus = 0; bus < MAX_BUS; bus++) {
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for (slot = 0; slot < MAX_SLOTS; slot++) {
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if (adapters[bus][slot] != -1) {
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counter++;
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kprintf("%d) Vendor ID: 0x%x Device Id: 0x%x\n",
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counter, adapters[bus][slot] & 0xffff,
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(adapters[bus][slot] & 0xffff0000) >> 16);
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for (i = 0; i < PCI_VENTABLE_LEN; i++) {
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if ((adapters[bus][slot] & 0xffff) ==
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(int)PciVenTable[i].VenId)
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kprintf("\tVendor is %s\n",
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PciVenTable[i].VenShort);
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}
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for (i = 0; i < PCI_DEVTABLE_LEN; i++) {
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if ((adapters[bus][slot] & 0xffff) ==
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(int)PciDevTable[i].VenId) {
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if (((adapters[bus][slot] & 0xffff0000) >> 16) ==
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PciDevTable[i].DevId) {
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kprintf
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("\tChip: %s ChipDesc: %s\n",
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PciDevTable[i].Chip,
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PciDevTable[i].ChipDesc);
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}
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}
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}
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}
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}
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}
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return 0;
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}
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#endif
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