fixed wrong filename for VHDL package
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1 changed files with 19 additions and 10 deletions
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@ -1,3 +1,6 @@
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-- -------------------------------------------------------------------
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-- Design:
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--
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-- Package for VHDL text output
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-- Package for VHDL text output
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--
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--
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-- Note:
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-- Note:
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@ -24,10 +27,10 @@
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-- >> report "DIN = "& str(DIN)& " expected 0101 " <<
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-- >> report "DIN = "& str(DIN)& " expected 0101 " <<
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-- >> severity Error; <<
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-- >> severity Error; <<
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--
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--
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--------------------------------------------------------------------------------
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-- -------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use std.textio.all;
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use std.textio.all;
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@ -98,18 +101,24 @@ package txt_util is
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-----------
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-----------
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-- read variable length string from input file
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-- read variable length string from input file
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procedure str_read(file in_file: TEXT;
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procedure str_read(
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res_string: out string);
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file in_file : TEXT;
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res_string : out string
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);
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-- print string to a file and start new line
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-- print string to a file and start new line
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procedure print(file out_file: TEXT;
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procedure print(
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new_string: in string);
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file out_file : TEXT;
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new_string : in string
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);
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-- print character to a file and start new line
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-- print character to a file and start new line
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procedure print(file out_file: TEXT;
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procedure print(
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char: in character);
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file out_file : TEXT;
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char : in character
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);
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end txt_util;
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end package;
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package body txt_util is
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package body txt_util is
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-- prints text to the screen
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-- prints text to the screen
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@ -529,4 +538,4 @@ package body txt_util is
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end if;
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end if;
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end loop;
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end loop;
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end str_write;
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end str_write;
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end txt_util;
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end package body;
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