yosys/tests/simple/arraycells.v


module array_test001(a, b, c, y);
	input a;
	input [31:0] b, c;
	output [31:0] y;

	aoi12 p [31:0] (a, b, c, y);
endmodule

module aoi12(a, b, c, y);
	input a, b, c;
	output y;
	assign y = ~((a & b) | c);
endmodule
added tests for new verilog features 2014-06-07 12:18:00 +02:00
Renamed some of the test cases in tests/simple to avoid name collisions 2014-07-25 13:01:45 +02:00			`module array_test001(a, b, c, y);`
added tests for new verilog features 2014-06-07 12:18:00 +02:00			`input a;`
			`input [31:0] b, c;`
Fixed typo in tests/simple/arraycells.v 2017-01-04 12:39:01 +01:00			`output [31:0] y;`
added tests for new verilog features 2014-06-07 12:18:00 +02:00
			`aoi12 p [31:0] (a, b, c, y);`
			`endmodule`

			`module aoi12(a, b, c, y);`
			`input a, b, c;`
			`output y;`
			`assign y = ~((a & b) \| c);`
			`endmodule`