yosys/btor.ys

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#design should be loaded before executing
#high level synthesis
#################
#converting processes to cells
proc;
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opt; opt_const -mux_undef; opt;
rename -hide;;;
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#converting pmux to mux
techmap -map techlibs/common/pmux2mux.v;
opt;
#converting asyn memory write to syn memory
memory_dff;
opt;
#flatten design
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flatten;;;
#cell output to be a single wire
splitnets -driver;
opt;;;
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#writing btor
write_btor design.btor;