yosys/passes/sat/example.ys

read_verilog example.v
techmap; opt; abc; opt
sat_solve -set y 1'b1
Added SAT generator and simple sat_solve command 2013-06-07 13:59:13 +02:00			`read_verilog example.v`
Improved sat generator and sat_solve pass 2013-06-07 14:37:33 +02:00			`techmap; opt; abc; opt`
Improved auto-detection of -show signals in sat_solve 2013-06-08 09:34:36 +02:00			`sat_solve -set y 1'b1`