yosys/btor.ys

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#design should be loaded before executing
#set the: hierarchy -top <module_top>
#set the: hierarchy -libdir <dir>
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#high level synthesis
#################
#converting processes to cells
proc;
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opt; opt_const -mux_undef; opt;
rename -hide;;;
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#converting pmux to mux
techmap -map techlibs/common/pmux2mux.v;;
memory -nomap;;
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#flatten design
flatten;;
#converting asyn memory write to syn memory
memory_unpack;
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#cell output to be a single wire
splitnets -driver;
opt;;;
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#writing btor
write_btor design.btor;