From d6feb4b43e6082d3b3a240160086c02295b0af04 Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Sun, 16 Oct 2016 22:53:43 -0700 Subject: [PATCH 1/5] greenpak4: Changed parameters for GP_SYSRESET --- techlibs/greenpak4/cells_sim.v | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 6ae9ae79..8515b985 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -409,7 +409,8 @@ endmodule //keep constraint needed to prevent optimization since we have no outputs (* keep *) module GP_SYSRESET(input RST); - parameter RESET_MODE = "RISING"; + parameter RESET_MODE = "EDGE"; + parameter EDGE_SPEED = 4; //cannot simulate whole system reset From a818472f0c1a5baa8fb6ba6f4b9a4340058e3616 Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Tue, 18 Oct 2016 19:33:26 -0700 Subject: [PATCH 2/5] greenpak4: added model for GP_EDGEDET block --- techlibs/greenpak4/cells_sim.v | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 8515b985..8a1794fc 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -241,6 +241,16 @@ module GP_DFFSRI(input D, CLK, nSR, output reg nQ); end endmodule +module GP_EDGEDET(input IN, output reg OUT); + + parameter EDGE_DIRECTION = "RISING"; + parameter DELAY_STEPS = 1; + parameter GLITCH_FILTER = 0; + + //not implemented for simulation + +endmodule + module GP_IBUF(input IN, output OUT); assign OUT = IN; endmodule From 091d32b563ecdd9e5a3377811fdd2411dc9fd1bc Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Tue, 18 Oct 2016 19:53:19 -0700 Subject: [PATCH 3/5] Added GLITCH_FILTER parameter to GP_DELAY --- techlibs/greenpak4/cells_sim.v | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 8a1794fc..668c6982 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -131,9 +131,8 @@ endmodule module GP_DELAY(input IN, output reg OUT); parameter DELAY_STEPS = 1; - - //TODO: additional delay/glitch filter mode - + parameter GLITCH_FILTER = 0; + initial OUT = 0; generate From e78fa157a3decfc6e595089c7d73b9cca785b252 Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Tue, 18 Oct 2016 20:42:44 -0700 Subject: [PATCH 4/5] greenpak4: Added GP_PGEN cell definition --- techlibs/greenpak4/cells_sim.v | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 668c6982..76bf058d 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -305,6 +305,27 @@ module GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg endmodule +module GP_PGEN(input wire nRST, input wire CLK, output reg OUT); + initial OUT = 0; + parameter PATTERN_DATA = 16'h0; + parameter PATTERN_LEN = 4'd16; + + reg[3:0] count = 0; + always @(posedge CLK) begin + if(!nRST) + OUT <= PATTERN_DATA[0]; + + else begin + count <= count + 1; + OUT <= PATTERN_DATA[count]; + + if( (count + 1) == PATTERN_LEN) + count <= 0; + end + end + +endmodule + module GP_POR(output reg RST_DONE); parameter POR_TIME = 500; From 1cca1563c64cd521a384a5df404dbccb3e06cb5c Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Tue, 18 Oct 2016 20:46:49 -0700 Subject: [PATCH 5/5] Fixed typo in last commit --- techlibs/greenpak4/cells_sim.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 76bf058d..80746be0 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -308,7 +308,7 @@ endmodule module GP_PGEN(input wire nRST, input wire CLK, output reg OUT); initial OUT = 0; parameter PATTERN_DATA = 16'h0; - parameter PATTERN_LEN = 4'd16; + parameter PATTERN_LEN = 5'd16; reg[3:0] count = 0; always @(posedge CLK) begin