Added "int ceil_log2(int)" function
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a75f94ec4a
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5 changed files with 58 additions and 10 deletions
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@ -260,7 +260,7 @@ struct BtorDumper
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if(it==std::end(line_ref))
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if(it==std::end(line_ref))
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{
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{
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++line_num;
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++line_num;
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int address_bits = ceil(log(memory->size)/log(2));
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int address_bits = ceil_log2(memory->size);
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str = stringf("%d array %d %d", line_num, memory->width, address_bits);
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str = stringf("%d array %d %d", line_num, memory->width, address_bits);
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line_ref[memory->name]=line_num;
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line_ref[memory->name]=line_num;
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f << stringf("%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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@ -272,7 +272,7 @@ struct BtorDumper
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int dump_memory_next(const RTLIL::Memory* memory)
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int dump_memory_next(const RTLIL::Memory* memory)
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{
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{
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auto mem_it = line_ref.find(memory->name);
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auto mem_it = line_ref.find(memory->name);
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int address_bits = ceil(log(memory->size)/log(2));
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int address_bits = ceil_log2(memory->size);
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if(mem_it==std::end(line_ref))
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if(mem_it==std::end(line_ref))
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{
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{
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log("can not write next of a memory that is not dumped yet\n");
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log("can not write next of a memory that is not dumped yet\n");
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@ -593,18 +593,18 @@ struct BtorDumper
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bool l1_signed = cell->parameters.at(RTLIL::IdString("\\A_SIGNED")).as_bool();
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bool l1_signed = cell->parameters.at(RTLIL::IdString("\\A_SIGNED")).as_bool();
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//bool l2_signed = cell->parameters.at(RTLIL::IdString("\\B_SIGNED")).as_bool();
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//bool l2_signed = cell->parameters.at(RTLIL::IdString("\\B_SIGNED")).as_bool();
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int l1_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
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int l1_width = cell->parameters.at(RTLIL::IdString("\\A_WIDTH")).as_int();
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l1_width = pow(2, ceil(log(l1_width)/log(2)));
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l1_width = 1 << ceil_log2(l1_width);
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int l2_width = cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
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int l2_width = cell->parameters.at(RTLIL::IdString("\\B_WIDTH")).as_int();
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//log_assert(l2_width <= ceil(log(l1_width)/log(2)) );
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//log_assert(l2_width <= ceil_log2(l1_width)) );
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int l1 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\A")), l1_width);
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int l1 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\A")), l1_width);
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int l2 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), ceil(log(l1_width)/log(2)));
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int l2 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), ceil_log2(l1_width));
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int cell_output = ++line_num;
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int cell_output = ++line_num;
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str = stringf ("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type.str()).c_str(), l1_width, l1, l2);
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str = stringf ("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type.str()).c_str(), l1_width, l1, l2);
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f << stringf("%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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if(l2_width > ceil(log(l1_width)/log(2)))
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if(l2_width > ceil_log2(l1_width))
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{
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{
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int extra_width = l2_width - ceil(log(l1_width)/log(2));
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int extra_width = l2_width - ceil_log2(l1_width);
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l2 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), l2_width);
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l2 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), l2_width);
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++line_num;
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++line_num;
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str = stringf ("%d slice %d %d %d %d;6", line_num, extra_width, l2, l2_width-1, l2_width-extra_width);
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str = stringf ("%d slice %d %d %d %d;6", line_num, extra_width, l2, l2_width-1, l2_width-extra_width);
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@ -821,7 +821,7 @@ struct BtorDumper
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++line_num;
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++line_num;
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str = cell->parameters.at(RTLIL::IdString("\\MEMID")).decode_string();
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str = cell->parameters.at(RTLIL::IdString("\\MEMID")).decode_string();
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RTLIL::Memory *memory = module->memories.at(RTLIL::IdString(str.c_str()));
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RTLIL::Memory *memory = module->memories.at(RTLIL::IdString(str.c_str()));
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int address_bits = ceil(log(memory->size)/log(2));
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int address_bits = ceil_log2(memory->size);
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str = stringf("%d array %d %d", line_num, memory->width, address_bits);
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str = stringf("%d array %d %d", line_num, memory->width, address_bits);
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f << stringf("%s\n", str.c_str());
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f << stringf("%s\n", str.c_str());
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++line_num;
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++line_num;
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@ -124,6 +124,31 @@ void yosys_banner()
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log("\n");
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log("\n");
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}
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}
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int ceil_log2(int x)
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{
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if (x <= 0)
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return 0;
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int y = (x & (x - 1));
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y = (y | -y) >> 31;
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x |= (x >> 1);
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x |= (x >> 2);
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x |= (x >> 4);
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x |= (x >> 8);
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x |= (x >> 16);
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x >>= 1;
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x -= ((x >> 1) & 0x55555555);
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x = (((x >> 2) & 0x33333333) + (x & 0x33333333));
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x = (((x >> 4) + x) & 0x0f0f0f0f);
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x += (x >> 8);
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x += (x >> 16);
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x = x & 0x0000003f;
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return x - y;
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}
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std::string stringf(const char *fmt, ...)
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std::string stringf(const char *fmt, ...)
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{
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{
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std::string string;
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std::string string;
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@ -222,6 +222,7 @@ extern bool memhasher_active;
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inline void memhasher() { if (memhasher_active) memhasher_do(); }
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inline void memhasher() { if (memhasher_active) memhasher_do(); }
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void yosys_banner();
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void yosys_banner();
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int ceil_log2(int x);
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std::string stringf(const char *fmt, ...) YS_ATTRIBUTE(format(printf, 1, 2));
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std::string stringf(const char *fmt, ...) YS_ATTRIBUTE(format(printf, 1, 2));
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std::string vstringf(const char *fmt, va_list ap);
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std::string vstringf(const char *fmt, va_list ap);
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int readsome(std::istream &f, char *s, int n);
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int readsome(std::istream &f, char *s, int n);
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@ -1337,6 +1337,28 @@ void ezSAT::printInternalState(FILE *f) const
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fprintf(f, "--8<-- snap --8<--\n");
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fprintf(f, "--8<-- snap --8<--\n");
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}
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}
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static int clog2(int x)
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{
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int y = (x & (x - 1));
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y = (y | -y) >> 31;
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x |= (x >> 1);
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x |= (x >> 2);
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x |= (x >> 4);
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x |= (x >> 8);
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x |= (x >> 16);
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x >>= 1;
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x -= ((x >> 1) & 0x55555555);
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x = (((x >> 2) & 0x33333333) + (x & 0x33333333));
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x = (((x >> 4) + x) & 0x0f0f0f0f);
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x += (x >> 8);
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x += (x >> 16);
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x = x & 0x0000003f;
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return x - y;
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}
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int ezSAT::onehot(const std::vector<int> &vec, bool max_only)
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int ezSAT::onehot(const std::vector<int> &vec, bool max_only)
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{
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{
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// Mixed one-hot/binary encoding as described by Claessen in Sec. 4.2 of
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// Mixed one-hot/binary encoding as described by Claessen in Sec. 4.2 of
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@ -1350,7 +1372,7 @@ int ezSAT::onehot(const std::vector<int> &vec, bool max_only)
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formula.push_back(expression(OpOr, vec));
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formula.push_back(expression(OpOr, vec));
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// create binary vector
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// create binary vector
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int num_bits = ceil(log2(vec.size()));
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int num_bits = clog2(vec.size());
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std::vector<int> bits;
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std::vector<int> bits;
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for (int k = 0; k < num_bits; k++)
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for (int k = 0; k < num_bits; k++)
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bits.push_back(literal());
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bits.push_back(literal());
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@ -85,7 +85,7 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs
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fsm_data.state_bits = fsm_data.state_table.size();
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fsm_data.state_bits = fsm_data.state_table.size();
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} else
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} else
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if (encoding == "binary") {
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if (encoding == "binary") {
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int new_num_state_bits = ceil(log2(fsm_data.state_table.size()));
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int new_num_state_bits = ceil_log2(fsm_data.state_table.size());
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if (fsm_data.state_bits == new_num_state_bits) {
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if (fsm_data.state_bits == new_num_state_bits) {
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log(" existing encoding is already a packed binary encoding.\n");
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log(" existing encoding is already a packed binary encoding.\n");
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return;
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return;
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