From 2b062c48cb4405f4a1bb6bd49edaf687bbc2cc4e Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Sat, 13 Aug 2016 22:27:58 -0700 Subject: [PATCH 1/3] greenpak4: Renamed ports for better consistency (see azonenberg/openfpga:#6) --- techlibs/greenpak4/cells_sim.v | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index ca8556a8..ceec2869 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -275,15 +275,15 @@ module GP_POR(output reg RST_DONE); endmodule -module GP_RCOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC); +module GP_RCOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC); parameter PWRDN_EN = 0; parameter AUTO_PWRDN = 0; - parameter PRE_DIV = 1; + parameter HARDIP_DIV = 1; parameter FABRIC_DIV = 1; parameter OSC_FREQ = "25k"; - initial CLKOUT_PREDIV = 0; + initial CLKOUT_HARDIP = 0; initial CLKOUT_FABRIC = 0; //output dividers not implemented for simulation @@ -291,7 +291,7 @@ module GP_RCOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC) always begin if(PWRDN) begin - CLKOUT_PREDIV = 0; + CLKOUT_HARDIP = 0; CLKOUT_FABRIC = 0; end else begin @@ -306,21 +306,21 @@ module GP_RCOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC) #250; end - CLKOUT_PREDIV = ~CLKOUT_PREDIV; + CLKOUT_HARDIP = ~CLKOUT_HARDIP; CLKOUT_FABRIC = ~CLKOUT_FABRIC; end end endmodule -module GP_RINGOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC); +module GP_RINGOSC(input PWRDN, output reg CLKOUT_HARDIP, output reg CLKOUT_FABRIC); parameter PWRDN_EN = 0; parameter AUTO_PWRDN = 0; - parameter PRE_DIV = 1; + parameter HARDIP_DIV = 1; parameter FABRIC_DIV = 1; - initial CLKOUT_PREDIV = 0; + initial CLKOUT_HARDIP = 0; initial CLKOUT_FABRIC = 0; //output dividers not implemented for simulation @@ -328,13 +328,13 @@ module GP_RINGOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRI always begin if(PWRDN) begin - CLKOUT_PREDIV = 0; + CLKOUT_HARDIP = 0; CLKOUT_FABRIC = 0; end else begin //half period of 27 MHz #18.518; - CLKOUT_PREDIV = ~CLKOUT_PREDIV; + CLKOUT_HARDIP = ~CLKOUT_HARDIP; CLKOUT_FABRIC = ~CLKOUT_FABRIC; end end From 3b9756c6a3ae1d1f5b6e530d4b50e07710b44987 Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Sun, 14 Aug 2016 00:11:44 -0700 Subject: [PATCH 2/3] greenpak4: Added GP_DFFxI cells --- techlibs/greenpak4/cells_map.v | 26 +++++++++++++++++++++ techlibs/greenpak4/cells_sim.v | 42 ++++++++++++++++++++++++++++++++++ 2 files changed, 68 insertions(+) diff --git a/techlibs/greenpak4/cells_map.v b/techlibs/greenpak4/cells_map.v index b7d750ae..36d2d031 100644 --- a/techlibs/greenpak4/cells_map.v +++ b/techlibs/greenpak4/cells_map.v @@ -24,6 +24,32 @@ module GP_DFFR(input D, CLK, nRST, output reg Q); ); endmodule +module GP_DFFSI(input D, CLK, nSET, output reg Q); + parameter [0:0] INIT = 1'bx; + GP_DFFSRI #( + .INIT(INIT), + .SRMODE(1'b1), + ) _TECHMAP_REPLACE_ ( + .D(D), + .CLK(CLK), + .nSR(nSET), + .Q(Q) + ); +endmodule + +module GP_DFFRI(input D, CLK, nRST, output reg Q); + parameter [0:0] INIT = 1'bx; + GP_DFFSRI #( + .INIT(INIT), + .SRMODE(1'b0), + ) _TECHMAP_REPLACE_ ( + .D(D), + .CLK(CLK), + .nSR(nRST), + .Q(Q) + ); +endmodule + module GP_OBUFT(input IN, input OE, output OUT); GP_IOBUF _TECHMAP_REPLACE_ ( .IN(IN), diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index ceec2869..e99c0c82 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -165,6 +165,14 @@ module GP_DFF(input D, CLK, output reg Q); end endmodule +module GP_DFFI(input D, CLK, output reg Q); + parameter [0:0] INIT = 1'bx; + initial Q = INIT; + always @(posedge CLK) begin + Q <= ~D; + end +endmodule + module GP_DFFR(input D, CLK, nRST, output reg Q); parameter [0:0] INIT = 1'bx; initial Q = INIT; @@ -176,6 +184,17 @@ module GP_DFFR(input D, CLK, nRST, output reg Q); end endmodule +module GP_DFFRI(input D, CLK, nRST, output reg Q); + parameter [0:0] INIT = 1'bx; + initial Q = INIT; + always @(posedge CLK, negedge nRST) begin + if (!nRST) + Q <= 1'b1; + else + Q <= ~D; + end +endmodule + module GP_DFFS(input D, CLK, nSET, output reg Q); parameter [0:0] INIT = 1'bx; initial Q = INIT; @@ -187,6 +206,17 @@ module GP_DFFS(input D, CLK, nSET, output reg Q); end endmodule +module GP_DFFSI(input D, CLK, nSET, output reg Q); + parameter [0:0] INIT = 1'bx; + initial Q = INIT; + always @(posedge CLK, negedge nSET) begin + if (!nSET) + Q <= 1'b0; + else + Q <= ~D; + end +endmodule + module GP_DFFSR(input D, CLK, nSR, output reg Q); parameter [0:0] INIT = 1'bx; parameter [0:0] SRMODE = 1'bx; @@ -199,6 +229,18 @@ module GP_DFFSR(input D, CLK, nSR, output reg Q); end endmodule +module GP_DFFSRI(input D, CLK, nSR, output reg Q); + parameter [0:0] INIT = 1'bx; + parameter [0:0] SRMODE = 1'bx; + initial Q = INIT; + always @(posedge CLK, negedge nSR) begin + if (!nSR) + Q <= ~SRMODE; + else + Q <= ~D; + end +endmodule + module GP_IBUF(input IN, output OUT); assign OUT = IN; endmodule From 0b0ba964881ce2996ee2feb1a5ca91c21669f0f7 Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Sun, 14 Aug 2016 00:30:45 -0700 Subject: [PATCH 3/3] greenpak4: Changed name of inverted output ports for consistency --- techlibs/greenpak4/cells_map.v | 8 ++++---- techlibs/greenpak4/cells_sim.v | 30 +++++++++++++++--------------- 2 files changed, 19 insertions(+), 19 deletions(-) diff --git a/techlibs/greenpak4/cells_map.v b/techlibs/greenpak4/cells_map.v index 36d2d031..111a77a1 100644 --- a/techlibs/greenpak4/cells_map.v +++ b/techlibs/greenpak4/cells_map.v @@ -24,7 +24,7 @@ module GP_DFFR(input D, CLK, nRST, output reg Q); ); endmodule -module GP_DFFSI(input D, CLK, nSET, output reg Q); +module GP_DFFSI(input D, CLK, nSET, output reg nQ); parameter [0:0] INIT = 1'bx; GP_DFFSRI #( .INIT(INIT), @@ -33,11 +33,11 @@ module GP_DFFSI(input D, CLK, nSET, output reg Q); .D(D), .CLK(CLK), .nSR(nSET), - .Q(Q) + .nQ(nQ) ); endmodule -module GP_DFFRI(input D, CLK, nRST, output reg Q); +module GP_DFFRI(input D, CLK, nRST, output reg nQ); parameter [0:0] INIT = 1'bx; GP_DFFSRI #( .INIT(INIT), @@ -46,7 +46,7 @@ module GP_DFFRI(input D, CLK, nRST, output reg Q); .D(D), .CLK(CLK), .nSR(nRST), - .Q(Q) + .nQ(nQ) ); endmodule diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index e99c0c82..6ae9ae79 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -165,11 +165,11 @@ module GP_DFF(input D, CLK, output reg Q); end endmodule -module GP_DFFI(input D, CLK, output reg Q); +module GP_DFFI(input D, CLK, output reg nQ); parameter [0:0] INIT = 1'bx; - initial Q = INIT; + initial nQ = INIT; always @(posedge CLK) begin - Q <= ~D; + nQ <= ~D; end endmodule @@ -184,14 +184,14 @@ module GP_DFFR(input D, CLK, nRST, output reg Q); end endmodule -module GP_DFFRI(input D, CLK, nRST, output reg Q); +module GP_DFFRI(input D, CLK, nRST, output reg nQ); parameter [0:0] INIT = 1'bx; - initial Q = INIT; + initial nQ = INIT; always @(posedge CLK, negedge nRST) begin if (!nRST) - Q <= 1'b1; + nQ <= 1'b1; else - Q <= ~D; + nQ <= ~D; end endmodule @@ -206,14 +206,14 @@ module GP_DFFS(input D, CLK, nSET, output reg Q); end endmodule -module GP_DFFSI(input D, CLK, nSET, output reg Q); +module GP_DFFSI(input D, CLK, nSET, output reg nQ); parameter [0:0] INIT = 1'bx; - initial Q = INIT; + initial nQ = INIT; always @(posedge CLK, negedge nSET) begin if (!nSET) - Q <= 1'b0; + nQ <= 1'b0; else - Q <= ~D; + nQ <= ~D; end endmodule @@ -229,15 +229,15 @@ module GP_DFFSR(input D, CLK, nSR, output reg Q); end endmodule -module GP_DFFSRI(input D, CLK, nSR, output reg Q); +module GP_DFFSRI(input D, CLK, nSR, output reg nQ); parameter [0:0] INIT = 1'bx; parameter [0:0] SRMODE = 1'bx; - initial Q = INIT; + initial nQ = INIT; always @(posedge CLK, negedge nSR) begin if (!nSR) - Q <= ~SRMODE; + nQ <= ~SRMODE; else - Q <= ~D; + nQ <= ~D; end endmodule