diff --git a/README b/README index 307f594b..f0c9bc74 100644 --- a/README +++ b/README @@ -270,6 +270,11 @@ Verilog Attributes and non-standard features for everything that comes after the {* ... *} statement. (Reset by adding an empty {* *} statement.) +- The "assert" statement from SystemVerilog is supported in its most basic + form. In module context: "assert property ();" and within an + always block: "assert();". It is transformed to a $assert cell + that is supported by the "sat" and "write_btor" commands. + Workarounds for known build problems ====================================