diff --git a/misc/yosysjs/demo03.html b/misc/yosysjs/demo03.html index 36cc6cf4..c9386aee 100644 --- a/misc/yosysjs/demo03.html +++ b/misc/yosysjs/demo03.html @@ -24,16 +24,18 @@ endmodule

YosysJS Example Application #03

Your mission: Create a behavioral Verilog model for the following circuit:

- -

-

module top(input clk, reset, input [7:0] A, output reg [7:0] Y);
-  always @(posedge clock) begin
-    Y <= A | {4{reset}};
-  end
-endmodule

- -

-

 

+