stv0g/yosys
1
0
Fork 0
Code Issues Pull requests Releases Wiki Activity

Improvements and bugfixes in clk2fflogic

Browse source
This commit is contained in:
Clifford Wolf 2016-10-16 23:03:29 +02:00
parent 189fbd4cf8
commit 3a09d6bb65
1 changed files with 21 additions and 13 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

34
passes/sat/clk2fflogic.cc
View file

@ -58,7 +58,6 @@ struct Clk2fflogicPass : public Pass {
SigMap sigmap(module);
dict<SigBit, State> initbits;
pool<SigBit> del_initbits;
vector<Cell*> ffcells;
for (auto wire : module->wires())
if (wire->attributes.count("\\init") > 0)
@ -71,18 +70,15 @@ struct Clk2fflogicPass : public Pass {
initbits[initsig[i]] = initval[i];
}
for (auto cell : module->selected_cells())
if (cell->type.in("$dff"))
ffcells.push_back(cell);
for (auto cell : ffcells)
for (auto cell : vector<Cell*>(module->selected_cells()))
{
if (cell->type == "$dff")
if (cell->type.in("$dff", "$adff"))
{
bool clkpol = cell->parameters["\\CLK_POLARITY"].as_bool();
SigSpec clk = cell->getPort("\\CLK");
SigSpec past_clk = module->addWire(NEW_ID);
Wire *past_clk = module->addWire(NEW_ID);
past_clk->attributes["\\init"] = clkpol ? State::S1 : State::S0;
module->addFf(NEW_ID, clk, past_clk);
SigSpec sig_d = cell->getPort("\\D");
@ -91,7 +87,6 @@ struct Clk2fflogicPass : public Pass {
log("Replacing %s.%s (%s): CLK=%s, D=%s, Q=%s\n",
log_id(module), log_id(cell), log_id(cell->type),
log_signal(clk), log_signal(sig_d), log_signal(sig_q));
module->remove(cell);
SigSpec clock_edge_pattern;
@ -103,14 +98,28 @@ struct Clk2fflogicPass : public Pass {
clock_edge_pattern.append_bit(State::S0);
}
SigSpec clock_edge = module->Eqx(NEW_ID, {past_clk, clk}, clock_edge_pattern);
SigSpec clock_edge = module->Eqx(NEW_ID, {clk, SigSpec(past_clk)}, clock_edge_pattern);
Wire *past_d = module->addWire(NEW_ID, GetSize(sig_d));
Wire *past_q = module->addWire(NEW_ID, GetSize(sig_q));
module->addFf(NEW_ID, sig_d, past_d);
module->addFf(NEW_ID, sig_q, past_q);
module->addMux(NEW_ID, past_q, past_d, clock_edge, sig_q);
if (cell->type == "$adff")
{
SigSpec arst = cell->getPort("\\ARST");
SigSpec qval = module->Mux(NEW_ID, past_q, past_d, clock_edge);
Const rstval = cell->parameters["\\ARST_VALUE"];
if (cell->parameters["\\ARST_POLARITY"].as_bool())
module->addMux(NEW_ID, qval, rstval, arst, sig_q);
else
module->addMux(NEW_ID, rstval, qval, arst, sig_q);
}
else
{
module->addMux(NEW_ID, past_q, past_d, clock_edge, sig_q);
}
Const initval;
bool assign_initval = false;
@ -130,10 +139,9 @@ struct Clk2fflogicPass : public Pass {
past_q->attributes["\\init"] = initval;
}
module->remove(cell);
continue;
}
log_abort();
}
for (auto wire : module->wires())