stv0g/yosys
1
0
Fork 0
Code Issues Pull requests Releases Wiki Activity

Fixes in $alu SAT- and eval-models

Browse source
This commit is contained in:
Clifford Wolf 2014-09-03 13:39:46 +02:00
parent 635b922afe
commit 50ac284823
2 changed files with 5 additions and 6 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
kernel/consteval.h
View file

@ -178,8 +178,8 @@ struct ConstEval
RTLIL::SigSpec sig_co = cell->getPort("\\CO");
bool any_input_undef = !(sig_a.is_fully_def() && sig_b.is_fully_def() && sig_ci.is_fully_def() && sig_bi.is_fully_def());
sig_a.extend(SIZE(sig_y), signed_a);
sig_b.extend(SIZE(sig_y), signed_b);
sig_a.extend_u0(SIZE(sig_y), signed_a);
sig_b.extend_u0(SIZE(sig_y), signed_b);
bool carry = sig_ci[0] == RTLIL::S1;
bool b_inv = sig_bi[0] == RTLIL::S1;

7
kernel/satgen.h
View file

@ -934,9 +934,9 @@ struct SatGen
std::vector<int> undef_x = importUndefSigSpec(cell->getPort("\\X"), timestep);
std::vector<int> undef_co = importUndefSigSpec(cell->getPort("\\CO"), timestep);
extendSignalWidth(undef_a, undef_b, undef_y, cell, true);
extendSignalWidth(undef_a, undef_b, undef_x, cell, true);
extendSignalWidth(undef_a, undef_b, undef_co, cell, true);
extendSignalWidth(undef_a, undef_b, undef_y, cell);
extendSignalWidth(undef_a, undef_b, undef_x, cell);
extendSignalWidth(undef_a, undef_b, undef_co, cell);
std::vector<int> all_inputs_undef;
all_inputs_undef.insert(all_inputs_undef.end(), undef_a.begin(), undef_a.end());
@ -955,7 +955,6 @@ struct SatGen
undefGating(x, def_x, undef_x);
undefGating(co, def_co, undef_co);
}
log_ping();
return true;
}