From 6685ad436e971ff896b260a782fad1edd3accc89 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 27 Aug 2013 13:12:26 +0200 Subject: [PATCH 1/3] Added mapping to techlibs/xilinx7 testbench (exposes EDIF backend todos) --- techlibs/xilinx7/run_testbench.sh | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/techlibs/xilinx7/run_testbench.sh b/techlibs/xilinx7/run_testbench.sh index 970fef46..31da59eb 100644 --- a/techlibs/xilinx7/run_testbench.sh +++ b/techlibs/xilinx7/run_testbench.sh @@ -2,7 +2,7 @@ set -ex -XILINX_DIR=/opt/Xilinx/14.5/ISE_DS/ISE/ +XILINX_DIR=/opt/Xilinx/14.2/ISE_DS/ISE/ ../../yosys - <<- EOT # read design @@ -20,6 +20,7 @@ XILINX_DIR=/opt/Xilinx/14.5/ISE_DS/ISE/ # write netlist write_verilog -noattr testbench_synth.v + write_edif testbench_synth.edif EOT iverilog -o testbench_gold counter_tb.v counter.v @@ -35,7 +36,14 @@ else exit 1 fi -if [ "$*" = "-clean" ]; then - rm -f testbench_{synth.v,{gold,gate}{,.txt}} +if [ "$*" = "-map" ]; then + set -x + $XILINX_DIR/bin/lin64/edif2ngd testbench_synth.edif + $XILINX_DIR/bin/lin64/ngdbuild -p xc7k70t testbench_synth +fi + +if [ "$*" = "-clean" ]; then + rm -rf netlist.lst _xmsgs/ + rm -f testbench_{synth,gold,gate}* fi From 2feee7415d012cf3a3bc08302d62aadc9d7ba100 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 27 Aug 2013 14:22:11 +0200 Subject: [PATCH 2/3] Improved edif backend --- backends/edif/edif.cc | 26 ++++++++++++++++++-------- 1 file changed, 18 insertions(+), 8 deletions(-) diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index a3231107..8bf2bbc2 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -196,21 +196,31 @@ struct EdifBackend : public Backend { dir = "INPUT"; else if (!wire->port_input) dir = "OUTPUT"; - for (int i = 0; i < wire->width; i++) { - std::string portname = wire->width > 1 ? stringf("%s[%d]", RTLIL::id2cstr(wire->name), - i+wire->start_offset) : RTLIL::id2cstr(wire->name); - fprintf(f, " (port %s (direction %s))\n", edif_names(portname).c_str(), dir); - RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire, 1, i)); - net_join_db[sig].insert(stringf("(portRef %s)", edif_names(portname).c_str())); + if (wire->width == 1) { + fprintf(f, " (port %s (direction %s))\n", EDIF_NAME(wire->name), dir); + RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire)); + net_join_db[sig].insert(stringf("(portRef %s)", EDIF_NAME(wire->name))); + } else { + fprintf(f, " (port (array %s %d) (direction %s))\n", EDIF_NAME(wire->name), wire->width, dir); + for (int i = 0; i < wire->width; i++) { + RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire, 1, i)); + net_join_db[sig].insert(stringf("(portRef (member %s %d))", EDIF_NAME(wire->name), i)); + } } } fprintf(f, " )\n"); fprintf(f, " (contents\n"); for (auto &cell_it : module->cells) { RTLIL::Cell *cell = cell_it.second; - fprintf(f, " (instance %s (viewRef VIEW_NETLIST (cellRef %s%s)))\n", - EDIF_NAME(cell->name), EDIF_NAME(cell->type), + fprintf(f, " (instance %s\n", EDIF_NAME(cell->name)); + fprintf(f, " (viewRef VIEW_NETLIST (cellRef %s%s))", EDIF_NAME(cell->type), lib_cell_ports.count(cell->type) > 0 ? " (libraryRef LIB)" : ""); + for (auto &p : cell->parameters) + if (p.second.bits.size() <= 32 && RTLIL::SigSpec(p.second).is_fully_def()) + fprintf(f, "\n (property %s (integer %u))", EDIF_NAME(p.first), p.second.as_int()); + else + fprintf(f, "\n (property %s FIXME)", EDIF_NAME(p.first)); + fprintf(f, ")\n"); for (auto &p : cell->connections) { RTLIL::SigSpec sig = sigmap(p.second); sig.expand(); From 09e200797a5f1aca9cadf9300f09b3b56191c39d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 28 Aug 2013 08:48:49 +0200 Subject: [PATCH 3/3] Encode large (>32 bits) parameters as hex string in edif backend --- backends/edif/edif.cc | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index 8bf2bbc2..944e576a 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -216,10 +216,23 @@ struct EdifBackend : public Backend { fprintf(f, " (viewRef VIEW_NETLIST (cellRef %s%s))", EDIF_NAME(cell->type), lib_cell_ports.count(cell->type) > 0 ? " (libraryRef LIB)" : ""); for (auto &p : cell->parameters) - if (p.second.bits.size() <= 32 && RTLIL::SigSpec(p.second).is_fully_def()) + if (!p.second.str.empty()) + fprintf(f, "\n (property %s (string \"%s\"))", EDIF_NAME(p.first), p.second.str.c_str()); + else if (p.second.bits.size() <= 32 && RTLIL::SigSpec(p.second).is_fully_def()) fprintf(f, "\n (property %s (integer %u))", EDIF_NAME(p.first), p.second.as_int()); - else - fprintf(f, "\n (property %s FIXME)", EDIF_NAME(p.first)); + else { + std::string hex_string = ""; + for (size_t i = 0; i < p.second.bits.size(); i += 4) { + int digit_value = 0; + if (i+0 < p.second.bits.size() && p.second.bits.at(i+0) == RTLIL::State::S1) digit_value += 1; + if (i+1 < p.second.bits.size() && p.second.bits.at(i+1) == RTLIL::State::S1) digit_value += 2; + if (i+2 < p.second.bits.size() && p.second.bits.at(i+2) == RTLIL::State::S1) digit_value += 3; + if (i+3 < p.second.bits.size() && p.second.bits.at(i+3) == RTLIL::State::S1) digit_value += 4; + char digit_str[2] = { "0123456789abcdef"[digit_value], 0 }; + hex_string = std::string(digit_str) + hex_string; + } + fprintf(f, "\n (property %s (string \"%s\"))", EDIF_NAME(p.first), hex_string.c_str()); + } fprintf(f, ")\n"); for (auto &p : cell->connections) { RTLIL::SigSpec sig = sigmap(p.second);