small fix in xilinx/brams.v
This commit is contained in:
parent
07703bdac4
commit
7cc5192125
1 changed files with 5 additions and 5 deletions
|
@ -97,8 +97,8 @@ module \$__XILINX_RAMB18_SDP36 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN
|
|||
input [35:0] B1DATA;
|
||||
input [3:0] B1EN;
|
||||
|
||||
wire [15:0] A1ADDR_16 = {A1ADDR, 5'b0};
|
||||
wire [15:0] B1ADDR_16 = {B1ADDR, 5'b0};
|
||||
wire [13:0] A1ADDR_14 = {A1ADDR, 5'b0};
|
||||
wire [13:0] B1ADDR_14 = {B1ADDR, 5'b0};
|
||||
|
||||
wire [3:0] DIP, DOP;
|
||||
wire [31:0] DI, DO;
|
||||
|
@ -139,15 +139,15 @@ module \$__XILINX_RAMB18_SDP36 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN
|
|||
.DIPBDIP(DIP[3:2]),
|
||||
.DIPADIP(DIP[1:0]),
|
||||
|
||||
.ADDRARDADDR(A1ADDR_16),
|
||||
.ADDRARDADDR(A1ADDR_14),
|
||||
.CLKARDCLK(CLKPOL2 ? CLK2 : ~CLK2),
|
||||
.ENARDEN(|1),
|
||||
.REGCEAREGCE(|1),
|
||||
.RSTRAMARSTRAM(|0),
|
||||
.RSTREGARSTREG(|0),
|
||||
.WEA(4'b0),
|
||||
.WEA(2'b0),
|
||||
|
||||
.ADDRBWRADDR(B1ADDR_16),
|
||||
.ADDRBWRADDR(B1ADDR_14),
|
||||
.CLKBWRCLK(CLKPOL3 ? CLK3 : ~CLK3),
|
||||
.ENBWREN(|1),
|
||||
.REGCEB(|0),
|
||||
|
|
Loading…
Add table
Reference in a new issue