Added module->uniquify()

frontends/verific/verific.cc

@@ -603,9 +603,7 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
 
 		// log("  importing net %s.\n", net->Name());
 
-		std::string wire_name = RTLIL::escape_id(net->Name());
-		while (module->count_id(wire_name))
-			wire_name += "_";
+		RTLIL::IdString wire_name = module->uniquify(RTLIL::escape_id(net->Name()));
 		RTLIL::Wire *wire = module->addWire(wire_name);
 		import_attributes(wire->attributes, net);
 
@@ -627,9 +625,7 @@ static void import_netlist(RTLIL::Design *design, Netlist *nl, std::set<Netlist*
 		{
 			// log("  importing netbus %s.\n", netbus->Name());
 
-			std::string wire_name = RTLIL::escape_id(netbus->Name());
-			while (module->count_id(wire_name))
-				wire_name += "_";
+			RTLIL::IdString wire_name = module->uniquify(RTLIL::escape_id(netbus->Name()));
 			RTLIL::Wire *wire = module->addWire(wire_name, netbus->Size());
 			wire->start_offset = std::min(netbus->LeftIndex(), netbus->RightIndex());
 			import_attributes(wire->attributes, netbus);

kernel/rtlil.cc

@@ -1108,6 +1108,28 @@ void RTLIL::Module::swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2)
 	cells_[c2->name] = c2;
 }
 
+RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name)
+{
+	int index = 0;
+	return uniquify(name, index);
+}
+
+RTLIL::IdString RTLIL::Module::uniquify(RTLIL::IdString name, int &index)
+{
+	if (index == 0) {
+		if (count_id(name) == 0)
+			return name;
+		index++;
+	}
+
+	while (1) {
+		RTLIL::IdString new_name = stringf("%s_%d", name.c_str(), index);
+		if (count_id(new_name) == 0)
+			return new_name;
+		index++;
+	}
+}
+
 static bool fixup_ports_compare(const RTLIL::Wire *a, const RTLIL::Wire *b)
 {
 	if (a->port_id && !b->port_id)

kernel/rtlil.h

@@ -625,6 +625,9 @@ public:
 	void swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2);
 	void swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2);
 
+	RTLIL::IdString uniquify(RTLIL::IdString name);
+	RTLIL::IdString uniquify(RTLIL::IdString name, int &index);
+
 	RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1);
 	RTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other);
 

passes/cmds/splitnets.cc

@@ -46,10 +46,7 @@ struct SplitnetsWorker
 		if (format.size() > 1)
 			new_wire_name += format.substr(1, 1);
 
-		while (module->count_id(new_wire_name) > 0)
-			new_wire_name += "_";
-
-		RTLIL::Wire *new_wire = module->addWire(new_wire_name, width);
+		RTLIL::Wire *new_wire = module->addWire(module->uniquify(new_wire_name), width);
 		new_wire->port_id = wire->port_id;
 		new_wire->port_input = wire->port_input;
 		new_wire->port_output = wire->port_output;

passes/fsm/fsm_map.cc

@@ -163,11 +163,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 
 	// create state register
 
-	std::string state_wire_name = fsm_cell->parameters["\\NAME"].decode_string();
-	while (module->count_id(state_wire_name) > 0)
-		state_wire_name += "_";
-
-	RTLIL::Wire *state_wire = module->addWire(state_wire_name, fsm_data.state_bits);
+	RTLIL::Wire *state_wire = module->addWire(module->uniquify(fsm_cell->parameters["\\NAME"].decode_string()), fsm_data.state_bits);
 	RTLIL::Wire *next_state_wire = module->addWire(NEW_ID, fsm_data.state_bits);
 
 	RTLIL::Cell *state_dff = module->addCell(NEW_ID, "");