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Added more help messages

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This commit is contained in:
Clifford Wolf 2013-03-01 00:36:19 +01:00
parent cd71c70b4f
commit 7fccad92f7
9 changed files with 121 additions and 11 deletions
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2
README
View file

@ -213,6 +213,8 @@ TODOs / Open Bugs
- Implement mux-to-tribuf pass and rebalance mixed mux/tribuf trees
- Add commands 'delete' (remove objects) and 'attr' (get, set and remove attributes)
- TCL and Python interfaces to frontends, passes, backends and RTLIL
- Additional internal cell types: $pla and $lut

24
backends/autotest/autotest.cc
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@ -298,7 +298,29 @@ static void autotest(FILE *f, RTLIL::Design *design)
}
struct AutotestBackend : public Backend {
AutotestBackend() : Backend("autotest") { }
AutotestBackend() : Backend("autotest", "generate simple test benches") { }
virtual void help()
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" write_autotest [filename]\n");
log("\n");
log("Automatically create primitive verilog test benches for all modules in the\n");
log("design. The generated testbenches toggle the input pins of the module in\n");
log("a semi-random manner and dumps the resulting output signals.\n");
log("\n");
log("This can be used to check the synthesis results for simple circuits by\n");
log("comparing the testbench output for the input files and the synthesis results.\n");
log("\n");
log("The backend automatically detects clock signals. Additionally a signal can\n");
log("be forced to be interpreted as clock signal by setting the attribute\n");
log("'gentb_clock' on the signal.\n");
log("\n");
log("The attribute 'gentb_constant' can be used to force a signal to a constant\n");
log("value after initialization. This can e.g. be used to force a reset signal\n");
log("low in order to explore more inner states in a state machine.\n");
log("\n");
}
virtual void execute(FILE *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing AUTOTEST backend (auto-generate pseudo-random test benches).\n");

12
backends/ilang/ilang_backend.cc
View file

@ -295,7 +295,17 @@ void ILANG_BACKEND::dump_design(FILE *f, const RTLIL::Design *design)
}
struct IlangBackend : public Backend {
IlangBackend() : Backend("ilang") { }
IlangBackend() : Backend("ilang", "write design to ilang file") { }
virtual void help()
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" write_ilang [filename]\n");
log("\n");
log("Write the current design to an 'ilang' file. (ilang is a text representation\n");
log("of a design in yosys's internal format.)\n");
log("\n");
}
virtual void execute(FILE *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) {
log_header("Executing ILANG backend.\n");
extra_args(f, filename, args, 1);

26
backends/verilog/verilog_backend.cc
View file

@ -854,7 +854,31 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module)
} /* namespace */
struct VerilogBackend : public Backend {
VerilogBackend() : Backend("verilog") { }
VerilogBackend() : Backend("verilog", "write design to verilog file") { }
virtual void help()
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" write_verilog [options] [filename]\n");
log("\n");
log("Write the current design to a verilog file.\n");
log("\n");
log(" -norename\n");
log(" without this option all internal object names (the ones with a dollar\n");
log(" instead of a backslash prefix) are changed to short names in the\n");
log(" format '_<number>_'.\n");
log("\n");
log(" -noattr\n");
log(" with this option no attributes are included in the output\n");
log("\n");
log(" -attr2comment\n");
log(" with this option attributes are included as comments in the output\n");
log("\n");
log(" -noexpr\n");
log(" without this option all internal cells are converted to verilog\n");
log(" expressions.\n");
log("\n");
}
virtual void execute(FILE *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing Verilog backend.\n");

2
kernel/driver.cc
View file

@ -210,6 +210,8 @@ struct ShellPass : public Pass {
log("This command is the default action if nothing else has been specified\n");
log("on the command line.\n");
log("\n");
log("Press Ctrl-D to leave the interactive shell.\n");
log("\n");
}
virtual void execute(std::vector<std::string>, RTLIL::Design *design) {
shell(design);

5
kernel/register.cc
View file

@ -146,7 +146,7 @@ void Pass::call(RTLIL::Design *design, std::vector<std::string> args)
if (args.size() == 0 || args[0][0] == '#')
return;
if (pass_register.count(args[0]) == 0)
log_cmd_error("No such command: %s\n", args[0].c_str());
log_cmd_error("No such command: %s (type 'help' for a command overview)\n", args[0].c_str());
size_t orig_sel_stack_pos = design->selection_stack.size();
pass_register[args[0]]->execute(args, design);
@ -356,6 +356,9 @@ struct HelpPass : public Pass {
log("\n");
for (auto &it : REGISTER_INTERN::pass_register)
log(" %-20s %s\n", it.first.c_str(), it.second->short_help.c_str());
log("\n");
log("Type 'help <command>' for more information on a command.\n");
log("\n");
return;
}

2
passes/extract/extract.cc
View file

@ -248,6 +248,8 @@ struct ExtractPass : public Pass {
log("This pass operates on whole modules or selected cells from modules. Other\n");
log("selected entities (wires, etc.) are ignored.\n");
log("\n");
log("See 'help techmap' for a pass that does the opposite thing.\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{

19
passes/submod/submod.cc
View file

@ -239,7 +239,24 @@ struct SubmodWorker
};
struct SubmodPass : public Pass {
SubmodPass() : Pass("submod") { }
SubmodPass() : Pass("submod", "moving part of a module to a new submodle") { }
virtual void help()
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" submod [selection]\n");
log("\n");
log("This pass identifies all cells with the 'submod' attribute and moves them to\n");
log("a newly created module. The value of the attribute is used as name for the\n");
log("cell that replaces the group of cells with the same attribute value.\n");
log("\n");
log("This pass can be used to create a design hierarchy in flat design. This can\n");
log("be useful for analyzing or reverse-engineering a design.\n");
log("\n");
log("This pass only operates on completely selected modules with no processes\n");
log("or memories.\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing SUBMOD pass (moving cells to submodes as requested).\n");

40
passes/techmap/techmap.cc
View file

@ -48,8 +48,11 @@ static void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module
std::map<std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>>, RTLIL::Module*> techmap_cache;
static bool techmap_module(RTLIL::Module *module, RTLIL::Design *map)
static bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map)
{
if (!design->selected(module))
return false;
bool did_something = false;
std::vector<std::string> cell_names;
@ -64,6 +67,9 @@ static bool techmap_module(RTLIL::Module *module, RTLIL::Design *map)
RTLIL::Cell *cell = module->cells[cell_name];
if (!design->selected(module, cell))
continue;
if (map->modules.count(cell->type) == 0)
continue;
@ -157,7 +163,26 @@ static bool techmap_module(RTLIL::Module *module, RTLIL::Design *map)
}
struct TechmapPass : public Pass {
TechmapPass() : Pass("techmap") { }
TechmapPass() : Pass("techmap", "simple technology mapper") { }
virtual void help()
{
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" techmap [-map filename] [selection]\n");
log("\n");
log("This pass implements a very simple technology mapper than replaces cells in\n");
log("the design with implementations given in form of a verilog or ilang source\n");
log("file.\n");
log("\n");
log(" -map filename\n");
log(" the library of cell implementations to be used.\n");
log(" without this parameter a builtin library is used that\n");
log(" transform the internal RTL cells to the internal gate\n");
log(" library.\n");
log("\n");
log("See 'help extract' for a pass that does the opposite thing.\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing TECHMAP pass (map to technology primitives).\n");
@ -175,11 +200,14 @@ struct TechmapPass : public Pass {
}
extra_args(args, argidx, design);
RTLIL::Design *map = new RTLIL::Design;
FILE *f = filename.empty() ? fmemopen(stdcells_code, strlen(stdcells_code), "rt") : fopen(filename.c_str(), "rt");
if (f == NULL)
log_error("Can't open map file `%s'\n", filename.c_str());
Frontend::frontend_call(map, f, filename.empty() ? "<stdcells.v>" : filename, "verilog");
log_cmd_error("Can't open map file `%s'\n", filename.c_str());
RTLIL::Design *map = new RTLIL::Design;
Frontend::frontend_call(map, f, filename.empty() ? "<stdcells.v>" : filename,
(filename.size() > 3 && filename.substr(filename.size()-3) == ".il") ? "ilang" : "verilog");
fclose(f);
std::map<RTLIL::IdString, RTLIL::Module*> modules_new;
@ -194,7 +222,7 @@ struct TechmapPass : public Pass {
while (did_something) {
did_something = false;
for (auto &mod_it : design->modules)
if (techmap_module(mod_it.second, map))
if (techmap_module(design, mod_it.second, map))
did_something = true;
}