Spell check (by Larry Doolittle)

This commit is contained in:
Clifford Wolf 2015-08-14 10:56:05 +02:00
parent 80910d13a6
commit 84bf862f7c
63 changed files with 220 additions and 220 deletions

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@ -70,7 +70,7 @@ struct BtorDumper
CellTypes ct;
SigMap sigmap;
std::map<RTLIL::IdString, std::set<WireInfo,WireInfoOrder>> inter_wire_map;//<wire, dependency list> for maping the intermediate wires that are output of some cell
std::map<RTLIL::IdString, std::set<WireInfo,WireInfoOrder>> inter_wire_map;//<wire, dependency list> for mapping the intermediate wires that are output of some cell
std::map<RTLIL::IdString, int> line_ref;//mapping of ids to line_num of the btor file
std::map<RTLIL::SigSpec, int> sig_ref;//mapping of sigspec to the line_num of the btor file
int line_num;//last line number of btor file
@ -722,7 +722,7 @@ struct BtorDumper
//registers
else if(cell->type == "$dff" || cell->type == "$adff" || cell->type == "$dffsr")
{
//TODO: remodelling fo adff cells
//TODO: remodelling of adff cells
log("writing cell - %s\n", cstr(cell->type));
int output_width = cell->parameters.at(RTLIL::IdString("\\WIDTH")).as_int();
log(" - width is %d\n", output_width);

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@ -284,7 +284,7 @@ void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire)
f << stringf("[%d:%d] ", wire->width - 1 + wire->start_offset, wire->start_offset);
f << stringf("%s;\n", id(wire->name).c_str());
#else
// do not use Verilog-2k "outut reg" syntax in verilog export
// do not use Verilog-2k "output reg" syntax in Verilog export
std::string range = "";
if (wire->width != 1) {
if (wire->upto)

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@ -269,7 +269,7 @@ namespace AST
void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef, bool defer, bool autowire);
// parametric modules are supported directly by the AST library
// therfore we need our own derivate of RTLIL::Module with overloaded virtual functions
// therefore we need our own derivate of RTLIL::Module with overloaded virtual functions
struct AstModule : RTLIL::Module {
AstNode *ast;
bool nolatches, nomeminit, nomem2reg, mem2reg, lib, noopt, icells, autowire;

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@ -176,13 +176,13 @@ struct AST_INTERNAL::ProcessGenerator
RTLIL::Process *proc;
RTLIL::SigSpec outputSignals;
// This always points to the RTLIL::CaseRule beeing filled at the moment
// This always points to the RTLIL::CaseRule being filled at the moment
RTLIL::CaseRule *current_case;
// This map contains the replacement pattern to be used in the right hand side
// of an assignment. E.g. in the code "foo = bar; foo = func(foo);" the foo in the right
// hand side of the 2nd assignment needs to be replace with the temporary signal holding
// the value assigned in the first assignment. So when the first assignement is processed
// the value assigned in the first assignment. So when the first assignment is processed
// the according information is appended to subst_rvalue_from and subst_rvalue_to.
stackmap<RTLIL::SigBit, RTLIL::SigBit> subst_rvalue_map;
@ -192,7 +192,7 @@ struct AST_INTERNAL::ProcessGenerator
// signal that is used as input for the register that drives the signal foo.
stackmap<RTLIL::SigBit, RTLIL::SigBit> subst_lvalue_map;
// The code here generates a number of temprorary signal for each output register. This
// The code here generates a number of temporary signal for each output register. This
// map helps generating nice numbered names for all this temporary signals.
std::map<RTLIL::Wire*, int> new_temp_count;
@ -766,7 +766,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
// in the following big switch() statement there are some uses of
// Clifford's Device (http://www.clifford.at/cfun/cliffdev/). In this
// cases this variable is used to hold the type of the cell that should
// be instanciated for this type of AST node.
// be instantiated for this type of AST node.
std::string type_name;
current_filename = filename;
@ -775,7 +775,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
switch (type)
{
// simply ignore this nodes.
// they are eighter leftovers from simplify() or are referenced by other nodes
// they are either leftovers from simplify() or are referenced by other nodes
// and are only accessed here thru this references
case AST_TASK:
case AST_FUNCTION:
@ -1073,7 +1073,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
}
// generate cells for unary operations: $reduce_bool
// (this is actually just an $reduce_or, but for clearity a different cell type is used)
// (this is actually just an $reduce_or, but for clarity a different cell type is used)
if (0) { case AST_REDUCE_BOOL: type_name = "$reduce_bool"; }
{
RTLIL::SigSpec arg = children[0]->genRTLIL();
@ -1415,7 +1415,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
}
// this is a wrapper for AstNode::genRTLIL() when a specific signal width is requested and/or
// signals must be substituted before beeing used as input values (used by ProcessGenerator)
// signals must be substituted before being used as input values (used by ProcessGenerator)
// note that this is using some global variables to communicate this special settings to AstNode::genRTLIL().
RTLIL::SigSpec AstNode::genWidthRTLIL(int width, const dict<RTLIL::SigBit, RTLIL::SigBit> *new_subst_ptr)
{

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@ -41,7 +41,7 @@ YOSYS_NAMESPACE_BEGIN
using namespace AST;
using namespace AST_INTERNAL;
// convert the AST into a simpler AST that has all parameters subsitited by their
// convert the AST into a simpler AST that has all parameters substituted by their
// values, unrolled for-loops, expanded generate blocks, etc. when this function
// is done with an AST it can be converted into RTLIL using genRTLIL().
//
@ -167,13 +167,13 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
set_line_num(linenum);
// we do not look inside a task or function
// (but as soon as a task of function is instanciated we process the generated AST as usual)
// (but as soon as a task or function is instantiated we process the generated AST as usual)
if (type == AST_FUNCTION || type == AST_TASK) {
recursion_counter--;
return false;
}
// deactivate all calls to non-synthesis system taks
// deactivate all calls to non-synthesis system tasks
if ((type == AST_FCALL || type == AST_TCALL) && (str == "$display" || str == "$strobe" || str == "$monitor" || str == "$time" || str == "$stop" || str == "$finish" ||
str == "$dumpfile" || str == "$dumpvars" || str == "$dumpon" || str == "$dumpoff" || str == "$dumpall")) {
log_warning("Ignoring call to system %s %s at %s:%d.\n", type == AST_FCALL ? "function" : "task", str.c_str(), filename.c_str(), linenum);
@ -1085,7 +1085,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
goto apply_newNode;
}
// replace primitives with assignmens
// replace primitives with assignments
if (type == AST_PRIMITIVE)
{
if (children.size() < 2)
@ -2260,7 +2260,7 @@ void AstNode::expand_genblock(std::string index_var, std::string prefix, std::ma
name_map.swap(backup_name_map);
}
// rename stuff (used when tasks of functions are instanciated)
// rename stuff (used when tasks of functions are instantiated)
void AstNode::replace_ids(const std::string &prefix, const std::map<std::string, std::string> &rules)
{
if (type == AST_BLOCK)
@ -2588,7 +2588,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
return did_something;
}
// calulate memory dimensions
// calculate memory dimensions
void AstNode::meminfo(int &mem_width, int &mem_size, int &addr_bits)
{
log_assert(type == AST_MEMORY);

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@ -789,7 +789,7 @@ struct VerificPass : public Pass {
log("\n");
log(" verific -import [-gates] {-all | <top-module>..}\n");
log("\n");
log("Elaborate the design for the sepcified top modules, import to Yosys and\n");
log("Elaborate the design for the specified top modules, import to Yosys and\n");
log("reset the internal state of Verific. A gate-level netlist is created\n");
log("when called with -gates.\n");
log("\n");

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@ -340,7 +340,7 @@ struct VerilogDefaults : public Pass {
log("\n");
log(" verilog_defaults -add [options]\n");
log("\n");
log("Add the sepcified options to the list of default options to read_verilog.\n");
log("Add the specified options to the list of default options to read_verilog.\n");
log("\n");
log("\n");
log(" verilog_defaults -clear");

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@ -217,7 +217,7 @@ int main(int argc, char **argv)
printf(" print version information and exit\n");
printf("\n");
printf("The option -S is an shortcut for calling the \"synth\" command, a default\n");
printf("script for transforming the verilog input to a gate-level netlist. For example:\n");
printf("script for transforming the Verilog input to a gate-level netlist. For example:\n");
printf("\n");
printf(" yosys -o output.blif -S input.v\n");
printf("\n");

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@ -145,7 +145,7 @@ std::string cover_list_worker(std::string prefix, std::string first, T... rest)
// ------------------------------------------------------------
// simple timer for performance measurements
// toggle the '#if 1' to get a baseline for the perormance penalty added by the measurement
// toggle the '#if 1' to get a baseline for the performance penalty added by the measurement
struct PerformanceTimer
{
#if 1

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@ -199,7 +199,7 @@ namespace RTLIL
bool operator==(IdString rhs) const { return index_ == rhs.index_; }
bool operator!=(IdString rhs) const { return index_ != rhs.index_; }
// The methods below are just convinience functions for better compatibility with std::string.
// The methods below are just convenience functions for better compatibility with std::string.
bool operator==(const std::string &rhs) const { return str() == rhs; }
bool operator!=(const std::string &rhs) const { return str() != rhs; }

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@ -596,7 +596,7 @@ struct TclPass : public Pass {
log("The tcl command 'yosys -import' can be used to import all yosys\n");
log("commands directly as tcl commands to the tcl shell. The yosys\n");
log("command 'proc' is wrapped using the tcl command 'procs' in order\n");
log("to avoid a name collision with the tcl builting command 'proc'.\n");
log("to avoid a name collision with the tcl builtin command 'proc'.\n");
log("\n");
}
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {

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@ -29,7 +29,7 @@
class ezSAT
{
// each token (terminal or non-terminal) is represented by an interger number
// each token (terminal or non-terminal) is represented by an integer number
//
// the zero token:
// the number zero is not used as valid token number and is used to encode

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@ -54,7 +54,7 @@
\begin{document}
\title{Yosys Application Note 011: \\ Interactive Design Investigation}
\author{Clifford Wolf \\ Original Verision December 2013}
\author{Clifford Wolf \\ Original Version December 2013}
\maketitle
\begin{abstract}
@ -497,7 +497,7 @@ using them will get its own net label.
In this case however we would like to see the cells connected properly. This
can be achieved using the {\tt \%x} action, that broadens the selection, i.e.
for each selected wire it selects all cells connected to the wire and vice
versa. So {\tt show a:sumstuff \%x} yields the diagram schon in Fig.~\ref{sumprod_01}.
versa. So {\tt show a:sumstuff \%x} yields the diagram shown in Fig.~\ref{sumprod_01}.
\begin{figure}[t]
\includegraphics[width=\linewidth]{APPNOTE_011_Design_Investigation/sumprod_01.pdf}
@ -744,7 +744,7 @@ The {\tt -table} option can be used to create a truth table. For example:
2'11 1'0 | 2'00 2'00
2'11 1'1 | 2'xx 2'11
Assumend undef (x) value for the following singals: \s2
Assumed undef (x) value for the following signals: \s2
\end{verbatim}
}

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@ -89,7 +89,7 @@ This Application Note is based on GIT Rev. {\tt 082550f} from
We assume that the Verilog design is synthesizable and we also assume
that the design does not have multi-dimensional memories. As BTOR
implicitly initializes registers to zero value and memories stay
uninitilized, we assume that the Verilog design does
uninitialized, we assume that the Verilog design does
not contain initial blocks. For more details about the BTOR format,
please refer to~\cite{btor}.

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@ -7,7 +7,7 @@
% \end{fixme}
%
% \section{Synthesizing using a Cell Library in Liberty Format}
% \section{Reverse Engeneering the MOS6502 from an NMOS Transistor Netlist}
% \section{Reverse Engineering the MOS6502 from an NMOS Transistor Netlist}
% \section{Reconfigurable Coarse-Grain Synthesis using Intersynth}
This appendix contains copies of the Yosys application notes.

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@ -59,7 +59,7 @@ script.
\section{Internal Formats in Yosys}
Yosys uses two different internal formats. The first is used to store an abstract syntax tree (AST) of a verilog
Yosys uses two different internal formats. The first is used to store an abstract syntax tree (AST) of a Verilog
input file. This format is simply called {\it AST} and is generated by the Verilog Frontend. This data structure
is consumed by a subsystem called {\it AST Frontend}\footnote{In Yosys the term {\it pass} is only used to
refer to commands that operate on the RTLIL data structure.}. This AST Frontend then generates a design in Yosys'
@ -107,7 +107,7 @@ from the input file {\tt design.v} to a gate-level netlist {\tt synth.v} using t
described by the Liberty file \citeweblink{LibertyFormat} {\tt cells.lib}:
\begin{lstlisting}[language=sh,numbers=left,frame=single]
# read input file tpo internal representation
# read input file to internal representation
read_verilog design.v
# convert high-level behavioral parts ("processes") to d-type flip-flops and muxes

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@ -1,7 +1,7 @@
\chapter{Auxilary Libraries}
\chapter{Auxiliary Libraries}
The Yosys source distribution contains some auxilary libraries that are bundled
The Yosys source distribution contains some auxiliary libraries that are bundled
with Yosys.
\section{SHA1}

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@ -1,5 +1,5 @@
\chapter{Auxilary Programs}
\chapter{Auxiliary Programs}
Besides the main {\tt yosys} executable, the Yosys distribution contains a set
of additional helper programs.

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@ -116,7 +116,7 @@ value or a condition in the sensitivity list is triggered. A synthesis tool
must be able to transfer this representation into an appropriate datapath followed
by the appropriate types of register.
For example consider the following verilog code fragment:
For example consider the following Verilog code fragment:
\begin{lstlisting}[numbers=left,frame=single,language=Verilog]
always @(posedge clk)
@ -141,8 +141,8 @@ App.~\ref{chapter:sota}).
\subsection{Register-Transfer Level (RTL)}
On the Register-Transfer Level the design is represented by combinatorial data
paths and registers (usually d-type flip flops). The following verilog code fragment
is equivalent to the previous verilog example, but is in RTL representation:
paths and registers (usually d-type flip flops). The following Verilog code fragment
is equivalent to the previous Verilog example, but is in RTL representation:
\begin{lstlisting}[numbers=left,frame=single,language=Verilog]
assign tmp = a + b; // combinatorial data path
@ -162,7 +162,7 @@ detection and optimization, identification of memories or other larger building
and identification of shareable resources.
Note that RTL is the first abstraction level in which the circuit is represented as a
graph of circuit elements (registers and combinatorical cells) and signals. Such a graph,
graph of circuit elements (registers and combinatorial cells) and signals. Such a graph,
when encoded as list of cells and connections, is called a netlist.
RTL synthesis is easy as each circuit node element in the netlist can simply be replaced
@ -262,10 +262,10 @@ Verilog syntax. Only the following language constructs are used in this case:
\end{itemize}
Many tools (especially at the back end of the synthesis chain) only support
structural verilog as input. ABC is an example of such a tool. Unfortunately
structural Verilog as input. ABC is an example of such a tool. Unfortunately
there is no standard specifying what {\it Structural Verilog} actually is,
leading to some confusion about what syntax constructs are supported in
structural verilog when it comes to features such as attributes or multi-bit
structural Verilog when it comes to features such as attributes or multi-bit
signals.
\subsection{Expressions in Verilog}
@ -280,8 +280,8 @@ and many others (comparison operations, unary operator, etc.) can also be used.
During synthesis these operators are replaced by cells that implement the respective function.
Many FOSS tools that claim to be able to process Verilog in fact only support
basic structural verilog and simple expressions. Yosys can be used to convert
full featured synthesizable verilog to this simpler subset, thus enabling such
basic structural Verilog and simple expressions. Yosys can be used to convert
full featured synthesizable Verilog to this simpler subset, thus enabling such
applications to be used with a richer set of Verilog features.
\subsection{Behavioural Modelling}
@ -561,7 +561,7 @@ In order to guarantee reproducibility it is important to be able to re-run all
automatic steps in a design project with a fixed set of settings easily.
Because of this, usually all programs used in a synthesis flow can be
controlled using scripts. This means that all functions are available via
text commands. When such a tool provides a gui, this is complementary to,
text commands. When such a tool provides a GUI, this is complementary to,
and not instead of, a command line interface.
Usually a synthesis flow in an UNIX/Linux environment would be controlled by a

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@ -104,7 +104,7 @@ Multiplexers are generated by the Verilog HDL frontend for {\tt
from RTLIL::Process objects to logic.
The simplest multiplexer cell type is {\tt \$mux}. Cells of this type have a \B{WIDTH} parameter
and data inputs \B{A} and \B{B} and a data ouput \B{Y}, all of the specified width. This cell also
and data inputs \B{A} and \B{B} and a data output \B{Y}, all of the specified width. This cell also
has a single bit control input \B{S}. If \B{S} is 0 the value from the \B{A} input is sent to
the output, if it is 1 the value from the \B{B} input is sent to the output. So the {\tt \$mux}
cell implements the function \lstinline[language=Verilog]; Y = S ? B : A;.
@ -399,7 +399,7 @@ represent d-type flip-flops.
The cell types {\tt \$\_DFF\_NN0\_}, {\tt \$\_DFF\_NN1\_}, {\tt \$\_DFF\_NP0\_}, {\tt \$\_DFF\_NP1\_},
{\tt \$\_DFF\_PN0\_}, {\tt \$\_DFF\_PN1\_}, {\tt \$\_DFF\_PP0\_} and {\tt \$\_DFF\_PP1\_} implement
d-type flip-flops with asynchronous resets. The values in the table for these cell types relate to the
following verilog code template, where \lstinline[mathescape,language=Verilog];$RstEdge$; is \lstinline[language=Verilog];posedge;
following Verilog code template, where \lstinline[mathescape,language=Verilog];$RstEdge$; is \lstinline[language=Verilog];posedge;
if \lstinline[mathescape,language=Verilog];$RstLvl$; if \lstinline[language=Verilog];1;, and \lstinline[language=Verilog];negedge;
otherwise.

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@ -43,7 +43,7 @@ The following measures were taken to increase the confidence in the correctness
make test} is executed. During development of Yosys it was shown that this
collection of test cases is sufficient to catch most bugs. The following more
sophisticated test procedures only caught a few additional bugs. Whenever this
happend, an appropiate test case was added to the collection of small test
happened, an appropriate test case was added to the collection of small test
cases for {\tt make test} to ensure better testability of the feature in
question in the future.
@ -64,7 +64,7 @@ validate successfully using Formality.
\item VlogHammer \citeweblink{VlogHammer} is a set of scripts that
auto-generate a large collection of test cases\footnote{At the time of this
writing over 6600 test cases.} and synthesize them using Yosys and the
following freely available propritary synthesis tools.
following freely available proprietary synthesis tools.
\begin{itemize}
\item Xilinx Vivado WebPack (2013.2) \citeweblink{XilinxWebPACK}
\item Xilinx ISE (XST) WebPack (14.5) \citeweblink{XilinxWebPACK}

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@ -69,7 +69,7 @@ These are the only three cases in which it is allowed to propagate an undef
according to Sec.~5.1.10 of IEEE Std. 1364-2005 \cite{Verilog2005}.
The next two lines assume the value 0 for undef states. These two rules are only
used if no other subsitutions are possible in the current module. If other substitutions
used if no other substitutions are possible in the current module. If other substitutions
are possible they are performed first, in the hope that the `any' will change to
an undef value or a 1 and therefore the output can be set to undef.
@ -296,7 +296,7 @@ table altered to give the same performance without the external feedback path.
\item Entries in the transition table that yield the same output and only
differ in the value of a single control input bit are merged and the different bit is removed
from the sensitivity list (turned into a don't-care bit).
\item Constant inputs are removed and the transition table is alterered to give an unchanged behaviour.
\item Constant inputs are removed and the transition table is altered to give an unchanged behaviour.
\item Unused inputs are removed.
\end{itemize}

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@ -238,7 +238,7 @@ An RTLIL::Wire object has the following properties:
\end{itemize}
As with modules, the attributes can be Verilog attributes imported by the
Verilog frontend or attributes assigned by passees.
Verilog frontend or attributes assigned by passes.
In Yosys, busses (signal vectors) are represented using a single wire object
with a width > 1. So Yosys does not convert signal vectors to individual signals.
@ -412,7 +412,7 @@ Some passes refuse to operate on modules that still contain RTLIL::Process objec
presence of these objects in a module increases the complexity. Therefore the passes to translate
processes to a netlist of cells are usually called early in a synthesis script. The {\tt proc}
pass calls a series of other passes that together perform this conversion in a way that is suitable
for most synthesis taks.
for most synthesis tasks.
\subsection{RTLIL::Memory}

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@ -24,7 +24,7 @@ static void find_stub_nets(RTLIL::Design *design, RTLIL::Module *module, bool re
// count how many times a single-bit signal is used
std::map<RTLIL::SigBit, int> bit_usage_count;
// count ouput lines for this module (needed only for summary output at the end)
// count output lines for this module (needed only for summary output at the end)
int line_count = 0;
log("Looking for stub wires in module %s:\n", RTLIL::id2cstr(module->name));

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@ -248,7 +248,7 @@ passes). This architecture will simplify implementing additional HDL front
ends and/or additional synthesis passes.
Chapter~\ref{chapter:eval} contains a more detailed evaluation of Yosys using real-world
designes that are far out of reach for any of the other tools discussed in this appendix.
designs that are far out of reach for any of the other tools discussed in this appendix.
\vskip2cm
\begin{table}[h]

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@ -19,7 +19,7 @@
*
* The internal logic cell simulation library.
*
* This verilog library contains simple simulation models for the internal
* This Verilog library contains simple simulation models for the internal
* logic cells (_NOT_, _AND_, ...) that are generated by the default technology
* mapper (see "stdcells.v" in this directory) and expected by the "abc" pass.
*

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@ -5,7 +5,7 @@
Previous chapters outlined how HDL code is transformed into an RTL netlist. The
RTL netlist is still based on abstract coarse-grain cell types like arbitrary
width adders and even multipliers. This chapter covers how an RTL netlist is
transformed into a functionally equivialent netlist utililizing the cell types
transformed into a functionally equivalent netlist utilizing the cell types
available in the target architecture.
Technology mapping is often performed in two phases. In the first phase RTL cells

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@ -98,7 +98,7 @@ The lexer does little more than identifying all keywords and literals
recognised by the Yosys Verilog frontend.
\end{sloppypar}
The lexer keeps track of the current location in the verilog source code using
The lexer keeps track of the current location in the Verilog source code using
some global variables. These variables are used by the constructor of AST nodes
to annotate each node with the source code location it originated from.
@ -168,11 +168,11 @@ Created by the simplifier when an undeclared signal name is used. \\
\hline
%
{\tt AST\_PARASET} &
Parameter set in cell instanciation \\
Parameter set in cell instantiation \\
\hline
%
{\tt AST\_ARGUMENT} &
Port connection in cell instanciation \\
Port connection in cell instantiation \\
\hline
%
{\tt AST\_RANGE} &
@ -184,7 +184,7 @@ A literal value \\
\hline
%
{\tt AST\_CELLTYPE} &
The type of cell in cell instanciation \\
The type of cell in cell instantiation \\
\hline
%
{\tt AST\_IDENTIFIER} &
@ -251,8 +251,8 @@ The unary reduction operators \break
\hline
%
{\tt AST\_REDUCE\_BOOL} &
Conversion from multi-bit value to boolian value
(equivialent to {\tt AST\_REDUCE\_OR}) \\
Conversion from multi-bit value to boolean value
(equivalent to {\tt AST\_REDUCE\_OR}) \\
\hline
%
{\tt AST\_SHIFT\_LEFT},
@ -327,7 +327,7 @@ An \lstinline[language=Verilog];assign; statement \\
\hline
%
{\tt AST\_CELL} &
A cell instanciation \\
A cell instantiation \\
\hline
%
{\tt AST\_PRIMITIVE} &
@ -359,7 +359,7 @@ and the default case respectively \\
\hline
%
{\tt AST\_FOR} &
A \lstinline[language=Verilog];for;-loop witn an
A \lstinline[language=Verilog];for;-loop with an
\lstinline[language=Verilog];always;- or
\lstinline[language=Verilog];initial;-block \\
\hline
@ -470,7 +470,7 @@ This produces an AST that is fairly easy to convert to the RTLIL format.
\subsection{Generating RTLIL}
After AST simplification, the \lstinline[language=C++]{AST::AstNode::genRTLIL()} method of each {\tt AST\_MODULE} node
in the AST is called. This initiates a recursive process that generates equivialent RTLIL data for the AST data.
in the AST is called. This initiates a recursive process that generates equivalent RTLIL data for the AST data.
The \lstinline[language=C++]{AST::AstNode::genRTLIL()} method returns an \lstinline[language=C++]{RTLIL::SigSpec} structure.
For nodes that represent expressions (operators, constants, signals, etc.), the cells needed to implement the calculation
@ -641,7 +641,7 @@ A pointer to a \lstinline[language=C++]{RTLIL::CaseRule} object. Initially this
generated \lstinline[language=C++]{RTLIL::Process}.
\end{itemize}
As the algorithm runs these variables are continously modified as well as pushed
As the algorithm runs these variables are continuously modified as well as pushed
to the stack and later restored to their earlier values by popping from the stack.
On startup the ProcessGenerator generates a new
@ -703,7 +703,7 @@ the ProcessGenerator:
\item A new \lstinline[language=C++]{RTLIL::SwitchRule} object is generated, the selection expression is evaluated using
\lstinline[language=C++]{AST::AstNode::genRTLIL()} (with the use of \lstinline[language=C++]{subst_rvalue_from} and
\lstinline[language=C++]{subst_rvalue_to}) and added to the \lstinline[language=C++]{RTLIL::SwitchRule} object and the
obect is added to the \lstinline[language=C++]{current_case}.
object is added to the \lstinline[language=C++]{current_case}.
%
\item All lvalues assigned to within the {\tt AST\_CASE} node using blocking assignments are collected and
saved in the local variable \lstinline[language=C++]{this_case_eq_lvalue}.
@ -837,7 +837,7 @@ as sr-latches or d-latches, without having to extend the actual Verilog frontend
\begin{fixme}
Add some information on the generation of {\tt \$memrd} and {\tt \$memwr} cells
and how they are processsed in the {\tt memory} pass.
and how they are processed in the {\tt memory} pass.
\end{fixme}
\section{Synthesizing Parametric Designs}

View File

@ -245,7 +245,7 @@ show -color red @cone_ab -color magenta @cone_a -color blue @cone_b
\begin{itemize}
\item
The {\tt techmap} command replaces cells in the design with implementations given
as verilog code (called ``map files''). It can replace Yosys' internal cell
as Verilog code (called ``map files''). It can replace Yosys' internal cell
types (such as {\tt \$or}) as well as user-defined cell types.
\medskip\item
Verilog parameters are used extensively to customize the internal cell types.
@ -480,7 +480,7 @@ cells in ASICS or dedicated carry logic in FPGAs.
\subsubsection{Intro to coarse-grain synthesis}
\begin{frame}[fragile]{\subsubsecname}
In coarse-grain synthesis the target architecure has cells of the same
In coarse-grain synthesis the target architecture has cells of the same
complexity or larger complexity than the internal RTL representation.
For example:
@ -558,7 +558,7 @@ $\downarrow$ & $\downarrow$ \\
\begin{frame}{\subsubsecname}
\scriptsize
Often a coarse-grain element has a constant bit-width, but can be used to
implement oprations with a smaller bit-width. For example, a 18x25-bit multiplier
implement operations with a smaller bit-width. For example, a 18x25-bit multiplier
can also be used to implement 16x20-bit multiplication.
\bigskip
@ -821,7 +821,7 @@ scripts as well as in reverse engineering and analysis.
\item {\bf Behavioral changes} \\
Commands such as {\tt techmap} can be used to make behavioral changes to the design, for example
changing asynchonous resets to synchronous resets. This has applications in design space exploration
changing asynchronous resets to synchronous resets. This has applications in design space exploration
(evaluation of various architectures for one circuit).
\end{itemize}
\end{frame}
@ -877,7 +877,7 @@ endmodule
\begin{frame}{\subsecname}
\begin{itemize}
\item A lot can be achived in Yosys just with the standard set of commands.
\item A lot can be achieved in Yosys just with the standard set of commands.
\item The commands {\tt techmap} and {\tt extract} can be used to prototype many complex synthesis tasks.
\end{itemize}

View File

@ -34,7 +34,7 @@ are connected.
\item
Commands such as {\tt submod}, {\tt expose}, {\tt splice}, \dots can be used
to transform the design into an equivialent design that is easier to analyse.
to transform the design into an equivalent design that is easier to analyse.
\item
Commands such as {\tt eval} and {\tt sat} can be used to investigate the
@ -102,7 +102,7 @@ Symbolic Model Checking (SMC) is used to formally prove that a circuit has
(or has not) a given property.
\bigskip
One appliction is Formal Equivalence Checking: Proving that two circuits
One application is Formal Equivalence Checking: Proving that two circuits
are identical. For example this is a very useful feature when debugging custom
passes in Yosys.
@ -143,11 +143,11 @@ rename test test_mapped
# apply the techmap only to test_mapped
techmap -map techmap_01_map.v test_mapped
# create a miter circuit to test equivialence
# create a miter circuit to test equivalence
miter -equiv -make_assert -make_outputs test_orig test_mapped miter
flatten miter
# run equivialence check
# run equivalence check
sat -verify -prove-asserts -show-inputs -show-outputs miter
\end{lstlisting}

View File

@ -9,9 +9,9 @@ rename test test_mapped
# apply the techmap only to test_mapped
techmap -map ../PRESENTATION_ExSyn/techmap_01_map.v test_mapped
# create a miter circuit to test equivialence
# create a miter circuit to test equivalence
miter -equiv -make_assert -make_outputs test_orig test_mapped miter
flatten miter
# run equivialence check
# run equivalence check
sat -verify -prove-asserts -show-inputs -show-outputs miter

View File

@ -216,7 +216,7 @@ proc; opt; memory; opt_const;; fsm;;
\begin{frame}{\subsecname}
Usually it does not hurt to call {\tt opt} after each regular command in the
synthesis script. But it increases the synthesis time, so it is favourable
to only call {\tt opt} when an improvement can be archieved.
to only call {\tt opt} when an improvement can be achieved.
\bigskip
The designs in {\tt yosys-bigsim} are a good playground for experimenting with
@ -320,7 +320,7 @@ fsm_map # unless got option -nomap
\end{frame}
\begin{frame}{\subsecname{} -- details}
Some details on the most importand commands from the {\tt fsm\_*} group:
Some details on the most important commands from the {\tt fsm\_*} group:
\bigskip
The {\tt fsm\_detect} command identifies FSM state registers and marks them

View File

@ -31,12 +31,12 @@
\only<3>{Netlists}%
\only<4>{Hardware Description Languages (HDLs)}}
\only<1>{
Graphical representation of the circtuit topology. Circuit elements
are represented by symbols and electrical connections by lines. The gometric
Graphical representation of the circuit topology. Circuit elements
are represented by symbols and electrical connections by lines. The geometric
layout is for readability only.
}%
\only<2>{
The actual physical geometry of the device (PCB or ASIC manufracturing masks).
The actual physical geometry of the device (PCB or ASIC manufacturing masks).
This is the final product of the design process.
}%
\only<3>{
@ -86,7 +86,7 @@
}%
\only<4>{
List of registers (flip-flops) and logic functions that calculate the next state from the previous one. Usually
a netlist utilizing high-level cells such as adders, multiplieres, multiplexer, etc.
a netlist utilizing high-level cells such as adders, multipliers, multiplexer, etc.
}%
\only<5>{
Netlist of single-bit registers and basic logic gates (such as AND, OR,
@ -95,7 +95,7 @@
}%
\only<6>{
Netlist of cells that actually are available on the target architecture
(such as CMOS gates in an ASCI or LUTs in an FPGA). Optimized for
(such as CMOS gates in an ASIC or LUTs in an FPGA). Optimized for
area, power, and/or speed (static timing or number of logic levels).
}%
\only<7>{
@ -155,7 +155,7 @@ Things Yosys can do:
\begin{itemize}
\item Read and process (most of) modern Verilog-2005 code.
\item Perform all kinds of operations on netlist (RTL, Logic, Gate).
\item Perform logic optimiziations and gate mapping with ABC\footnote[frame]{\url{http://www.eecs.berkeley.edu/~alanmi/abc/}}.
\item Perform logic optimizations and gate mapping with ABC\footnote[frame]{\url{http://www.eecs.berkeley.edu/~alanmi/abc/}}.
\end{itemize}
\bigskip
@ -176,7 +176,7 @@ as Qflow\footnote[frame]{\url{http://opencircuitdesign.com/qflow/}} for ASIC des
\subsection{Yosys Data- and Control-Flow}
\begin{frame}{\subsecname}
A (usually short) synthesis script controlls Yosys.
A (usually short) synthesis script controls Yosys.
This scripts contain three types of commands:
\begin{itemize}
@ -658,7 +658,7 @@ endmodule
\subsection{Verification of Yosys}
\begin{frame}{\subsecname}
Contiously checking the correctness of Yosys and making sure that new features
Continuously checking the correctness of Yosys and making sure that new features
do not break old ones is a high priority in Yosys.
\bigskip
@ -697,7 +697,7 @@ the other tools used as external reference where found and reported so far.
\begin{frame}{\subsecname{} -- yosys-bigsim}
yosys-bigsim is a collection of real-world open-source Verilog designs and test
benches. yosys-bigsim compares the testbench outpus of simulations of the original
benches. yosys-bigsim compares the testbench outputs of simulations of the original
Verilog code and synthesis results.
\bigskip
@ -721,7 +721,7 @@ The following designs are included in yosys-bigsim (excerpt):
\begin{frame}{\subsecname}
\begin{itemize}
\item Cost (also applies to ``free as in free beer'' solutions)
\item Availablity and Reproducability
\item Availability and Reproducibility
\item Framework- and all-in-one-aspects
\item Educational Tool
\end{itemize}
@ -739,7 +739,7 @@ the cost for the design tools needed to design the mask layouts. Open Source
ASIC flows are an important enabler for ASIC-level Open Source Hardware.
\bigskip
\item Availablity and Reproducability: \smallskip\par
\item Availability and Reproducibility: \smallskip\par
If you are a researcher who is publishing, you want to use tools that everyone
else can also use. Even if most universities have access to all major
commercial tools, you usually do not have easy access to the version that was
@ -757,9 +757,9 @@ basic functionality. Extensibility was one of Yosys' design goals.
\bigskip
\item All-in-one: \smallskip\par
Because of the framework characterisitcs of Yosys, an increasing number of features
Because of the framework characteristics of Yosys, an increasing number of features
become available in one tool. Yosys not only can be used for circuit synthesis but
also for formal equivialence checking, SAT solving, and for circuit analysis, to
also for formal equivalence checking, SAT solving, and for circuit analysis, to
name just a few other application domains. With proprietary software one needs to
learn a new tool for each of this applications.
\end{itemize}
@ -768,7 +768,7 @@ learn a new tool for each of this applications.
\begin{frame}{\subsecname{} -- 3/3}
\begin{itemize}
\item Educational Tool: \smallskip\par
Propritaery synthesis tools are at times very secretive about their inner
Proprietary synthesis tools are at times very secretive about their inner
workings. They often are ``black boxes''. Yosys is very open about its
internals and it is easy to observe the different steps of synthesis.
\end{itemize}
@ -789,8 +789,8 @@ copyright notice and this permission notice appear in all copies.
\begin{itemize}
\item Synthesis of final production designs
\item Pre-production synthesis (trial runs before investing in other tools)
\item Convertion of full-featured Verilog to simple Verilog
\item Convertion of Verilog to other formats (BLIF, BTOR, etc)
\item Conversion of full-featured Verilog to simple Verilog
\item Conversion of Verilog to other formats (BLIF, BTOR, etc)
\item Demonstrating synthesis algorithms (e.g. for educational purposes)
\item Framework for experimenting with new algorithms
\item Framework for building custom flows\footnote[frame]{Not limited to synthesis
@ -908,7 +908,7 @@ control logic because it is simpler than setting up a commercial flow.
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\subsection{Documentation, Downloads, Contatcs}
\subsection{Documentation, Downloads, Contacts}
\begin{frame}{\subsecname}
\begin{itemize}
@ -916,7 +916,7 @@ control logic because it is simpler than setting up a commercial flow.
\smallskip\hskip1cm\url{http://www.clifford.at/yosys/}
\bigskip
\item Manual, Command Reference, Appliction Notes: \\
\item Manual, Command Reference, Application Notes: \\
\smallskip\hskip1cm\url{http://www.clifford.at/yosys/documentation.html}
\bigskip

View File

@ -124,7 +124,7 @@ has been executed.
\begin{frame}{\subsecname}
The RTLIL data structures are simple structs utilizing {\tt pool<>} and
{\tt dict<>} containers (drop-in replacementments for {\tt
{\tt dict<>} containers (drop-in replacements for {\tt
std::unordered\_set<>} and {\tt std::unordered\_map<>}).
\bigskip
@ -413,7 +413,7 @@ When modifying existing modules, stick to the following DOs and DON'Ts:
\item Use {\tt module->fixup\_ports()} after changing the {\tt port\_*} properties of wires.
\item You can safely remove cells or change the {\tt connetions} property of a cell, but be careful when
\item You can safely remove cells or change the {\tt connections} property of a cell, but be careful when
changing the size of the {\tt SigSpec} connected to a cell port.
\item Use the {\tt SigMap} helper class (see next slide) when you need a unique handle for each signal bit.

View File

@ -16,7 +16,7 @@ library to a target architecture.
use the specified ABC script file instead of the default script.
if <file> starts with a plus sign (+), then the rest of the filename
string is interprated as the command string to be passed to ABC. the
string is interpreted as the command string to be passed to ABC. The
leading plus sign is removed and all commas (,) in the string are
replaced with blanks before the string is passed to ABC.
@ -90,7 +90,7 @@ library to a target architecture.
-keepff
set the "keep" attribute on flip-flop output wires. (and thus preserve
them, for example for equivialence checking.)
them, for example for equivalence checking.)
-nocleanup
when this option is used, the temporary files created by this pass
@ -156,7 +156,7 @@ This is just a shortcut for 'select -module <modname>'.
cd <cellname>
When no module with the specified name is found, but there is a cell
with the specified name in the current module, then this is equivialent
with the specified name in the current module, then this is equivalent
to 'cd <celltype>'.
cd ..
@ -183,8 +183,8 @@ in -purge mode between the commands.
\begin{lstlisting}[numbers=left,frame=single]
connect [-nomap] [-nounset] -set <lhs-expr> <rhs-expr>
Create a connection. This is equivialent to adding the statement 'assign
<lhs-expr> = <rhs-expr>;' to the verilog input. Per default, all existing
Create a connection. This is equivalent to adding the statement 'assign
<lhs-expr> = <rhs-expr>;' to the Verilog input. Per default, all existing
drivers for <lhs-expr> are unconnected. This can be overwritten by using
the -nounset option.
@ -216,8 +216,8 @@ This command does not operate on module with processes.
Wrappers are used in coarse-grain synthesis to wrap cells with smaller ports
in wrapper cells with a (larger) constant port size. I.e. the upper bits
of the wrapper outut are signed/unsigned bit extended. This command uses this
knowlege to rewire the inputs of the driven cells to match the output of
of the wrapper output are signed/unsigned bit extended. This command uses this
knowledge to rewire the inputs of the driven cells to match the output of
the driving cell.
-signed <cell_type> <port_name> <width_param>
@ -343,7 +343,7 @@ evaluated in the other design.
design -copy-to <name> [-as <new_mod_name>] [selection]
Copy modules from the current design into the soecified one.
Copy modules from the current design into the specified one.
\end{lstlisting}
\section{dff2dffe -- transform \$dff cells to \$dffe cells}
@ -365,7 +365,7 @@ $_DFF_P_, $_DFF_N_ and $_MUX_.
<external_gate_type> is the cell type name for a cell with an
identical interface to the <internal_gate_type>, except it
also has an high-active enable port 'E'.
Usually <external_gate_type> is an intemediate cell type
Usually <external_gate_type> is an intermediate cell type
that is then translated to the final type using 'techmap'.
\end{lstlisting}
@ -473,7 +473,7 @@ to work with the created equivalent checking module.
Do not match cells or signals that match the names in the file.
-encfile <file>
Match FSM encodings using the desiption from the file.
Match FSM encodings using the description from the file.
See 'help fsm_recode' for details.
Note: The circuit created by this command is not a miter (with something like
@ -585,8 +585,8 @@ outputs.
signal path at that wire.
-shared
only expose those signals that are shared ammong the selected modules.
this is useful for preparing modules for equivialence checking.
only expose those signals that are shared among the selected modules.
this is useful for preparing modules for equivalence checking.
-evert
also turn connections to instances of other modules to additional
@ -609,7 +609,7 @@ outputs.
This pass looks for subcircuits that are isomorphic to any of the modules
in the given map file and replaces them with instances of this modules. The
map file can be a verilog source file (*.v) or an ilang file (*.il).
map file can be a Verilog source file (*.v) or an ilang file (*.il).
-map <map_file>
use the modules in this file as reference. This option can be used
@ -638,11 +638,11 @@ map file can be a verilog source file (*.v) or an ilang file (*.il).
match. This option can be used multiple times.
-swap <needle_type> <port1>,<port2>[,...]
Register a set of swapable ports for a needle cell type.
Register a set of swappable ports for a needle cell type.
This option can be used multiple times.
-perm <needle_type> <port1>,<port2>[,...] <portA>,<portB>[,...]
Register a valid permutation of swapable ports for a needle
Register a valid permutation of swappable ports for a needle
cell type. This option can be used multiple times.
-cell_attr <attribute_name>
@ -657,7 +657,7 @@ map file can be a verilog source file (*.v) or an ilang file (*.il).
-ignore_param <cell_type> <parameter_name>
Do not use this parameter when matching cells.
This pass does not operate on modules with uprocessed processes in it.
This pass does not operate on modules with unprocessed processes in it.
(I.e. the 'proc' pass should be used first to convert processes to netlists.)
This pass can also be used for mining for frequent subcircuits. In this mode
@ -694,7 +694,7 @@ See 'help techmap' for a pass that does the opposite thing.
flatten [selection]
This pass flattens the design by replacing cells by their implementation. This
pass is very simmilar to the 'techmap' pass. The only difference is that this
pass is very similar to the 'techmap' pass. The only difference is that this
pass is using the current design as mapping library.
\end{lstlisting}
@ -704,7 +704,7 @@ pass is using the current design as mapping library.
freduce [options] [selection]
This pass performs functional reduction in the circuit. I.e. if two nodes are
equivialent, they are merged to one node and one of the redundant drivers is
equivalent, they are merged to one node and one of the redundant drivers is
disconnected. A subsequent call to 'clean' will remove the redundant drivers.
-v, -vv
@ -722,7 +722,7 @@ disconnected. A subsequent call to 'clean' will remove the redundant drivers.
operation. this is mostly used for debugging the freduce command.
This pass is undef-aware, i.e. it considers don't-care values for detecting
equivialent nodes.
equivalent nodes.
All selected wires are considered for rewiring. The selected cells cover the
circuit that is analyzed.
@ -734,7 +734,7 @@ circuit that is analyzed.
fsm [options] [selection]
This pass calls all the other fsm_* passes in a useful order. This performs
FSM extraction and optimiziation. It also calls opt_clean as needed:
FSM extraction and optimization. It also calls opt_clean as needed:
fsm_detect unless got option -nodetect
fsm_extract
@ -759,7 +759,7 @@ Options:
-expand, -norecode, -export, -nomap
enable or disable passes as indicated above
-encoding tye
-encoding type
-fm_set_fsm_file file
-encfile file
passed through to fsm_recode pass
@ -787,7 +787,7 @@ Signals can be protected from being detected by this pass by setting the
The fsm_extract pass is conservative about the cells that belong to a finite
state machine. This pass can be used to merge additional auxiliary gates into
the finate state machine.
the finite state machine.
\end{lstlisting}
\section{fsm\_export -- exporting FSMs to KISS2 files}
@ -936,7 +936,7 @@ determine the direction of the ports. The syntax for a port declaration is:
Input ports are specified with the 'i' prefix, output ports with the 'o'
prefix and inout ports with the 'io' prefix. The optional <num> specifies
the position of the port in the parameter list (needed when instanciated
the position of the port in the parameter list (needed when instantiated
using positional arguments). When <num> is not specified, the <portname> can
also contain wildcard characters.
@ -1085,7 +1085,7 @@ rules. A block ram description looks like this:
ports 1 1 # number of ports in each group
wrmode 1 0 # set to '1' if this groups is write ports
enable 4 0 # number of enable bits (for write ports)
transp 0 2 # transparatent (for read ports)
transp 0 2 # transparent (for read ports)
clocks 1 2 # clock configuration
clkpol 2 2 # clock polarity configuration
endbram
@ -1103,7 +1103,7 @@ and a value greater than 1 means configurable. All groups with the same value
greater than 1 share the same configuration bit.
Using the same bram name in different bram blocks will create different variants
of the bram. Verilog configration parameters for the bram are created as needed.
of the bram. Verilog configuration parameters for the bram are created as needed.
It is also possible to create variants by repeating statements in the bram block
and appending '@<label>' to the individual statements.
@ -1136,7 +1136,7 @@ It is possible to match against the following values with min/max rules:
dcells ....... number of cells in 'data-direction'
cells ........ total number of cells (acells*dcells*dups)
The interface for the created bram instances is dervived from the bram
The interface for the created bram instances is derived from the bram
description. Use 'techmap' to convert the created bram instances into
instances of the actual bram cells of your target architecture.
@ -1221,7 +1221,7 @@ $memwr cells. It is the counterpart to the memory_collect pass.
\begin{lstlisting}[numbers=left,frame=single]
miter -equiv [options] gold_name gate_name miter_name
Creates a miter circuit for equivialence checking. The gold- and gate- modules
Creates a miter circuit for equivalence checking. The gold- and gate- modules
must have the same interfaces. The miter circuit will have all inputs of the
two source modules, prefixed with 'in_'. The miter circuit has a 'trigger'
output that goes high if an output mismatch between the two source modules is
@ -1457,7 +1457,7 @@ d-type flip-flop cells.
\begin{lstlisting}[numbers=left,frame=single]
proc_init [selection]
This pass extracts the 'init' actions from processes (generated from verilog
This pass extracts the 'init' actions from processes (generated from Verilog
'initial' blocks) and sets the initial value to the 'init' attribute on the
respective wire.
\end{lstlisting}
@ -1513,12 +1513,12 @@ Read cells from liberty file as modules into current design.
set the specified attribute (to the value 1) on all loaded modules
\end{lstlisting}
\section{read\_verilog -- read modules from verilog file}
\section{read\_verilog -- read modules from Verilog file}
\label{cmd:read_verilog}
\begin{lstlisting}[numbers=left,frame=single]
read_verilog [options] [filename]
Load modules from a verilog file to the current design. A large subset of
Load modules from a Verilog file to the current design. A large subset of
Verilog-2005 is supported.
-sv
@ -1532,7 +1532,7 @@ Verilog-2005 is supported.
dump abstract syntax tree (after simplification)
-dump_vlog
dump ast as verilog code (after simplification)
dump ast as Verilog code (after simplification)
-yydebug
enable parser debug output
@ -1560,7 +1560,7 @@ Verilog-2005 is supported.
module or register.
-ppdump
dump verilog code after pre-processor
dump Verilog code after pre-processor
-nopp
do not run the pre-processor
@ -1600,7 +1600,7 @@ subsequent calls to 'read_verilog'.
Note that the Verilog frontend does a pretty good job of processing valid
verilog input, but has not very good error reporting. It generally is
recommended to use a simulator (for example icarus verilog) for checking
recommended to use a simulator (for example Icarus Verilog) for checking
the syntax of the code, rather than to rely on read_verilog for that.
\end{lstlisting}
@ -1716,7 +1716,7 @@ The following additional options can be used to set up a proof. If also -seq
is passed, a temporal induction proof is performed.