diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index c7f07e40..1f114a22 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -23,13 +23,13 @@ module BUFG(output O, input I);
   assign O = I;
 endmodule
 
-module OBUFT(output O, input I, T);
-  assign O = T ? 1'bz : I;
-endmodule
+// module OBUFT(output O, input I, T);
+//   assign O = T ? 1'bz : I;
+// endmodule
 
-module IOBUF(inout IO, output O, input I, T);
-  assign O = IO, IO = T ? 1'bz : I;
-endmodule
+// module IOBUF(inout IO, output O, input I, T);
+//   assign O = IO, IO = T ? 1'bz : I;
+// endmodule
 
 module INV(output O, input I);
   assign O = !I;