Merge pull request #157 from azonenberg/master

Added GP_ABUF cell, support for tri-state I/O buffers in GreenPak
This commit is contained in:
Clifford Wolf 2016-05-04 19:12:59 +02:00
commit 86add29072
5 changed files with 52 additions and 0 deletions

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@ -2,6 +2,7 @@
OBJS += techlibs/greenpak4/synth_greenpak4.o
OBJS += techlibs/greenpak4/greenpak4_counters.o
$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_extract.v))
$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_map.v))
$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/cells_sim.v))
$(eval $(call add_share_file,share/greenpak4,techlibs/greenpak4/gp_dff.lib))

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@ -0,0 +1,15 @@
//Wrapper module to patch up output of iopadmap
module GP_IOBUF(input IN, output OUT, input OE, inout IO);
GP_IBUF ibuf(
.IN(IO),
.OUT(OUT)
);
$_TBUF_ tbuf(
.A(IN),
.E(OE),
.Y(OUT)
);
endmodule

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@ -24,6 +24,15 @@ module GP_DFFR(input D, CLK, nRST, output reg Q);
);
endmodule
module GP_OBUFT(input IN, input OE, output OUT);
GP_IOBUF _TECHMAP_REPLACE_ (
.IN(IN),
.OE(OE),
.IO(OUT),
.OUT()
);
endmodule
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;

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@ -13,6 +13,14 @@ module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT);
assign OUT = INIT[{IN3, IN2, IN1, IN0}];
endmodule
module GP_ABUF(input wire IN, output wire OUT);
assign OUT = IN;
//cannot simulate mixed signal IP
endmodule
module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);
parameter BANDWIDTH = "HIGH";
@ -126,6 +134,15 @@ module GP_DFFSR(input D, CLK, nSR, output reg Q);
end
endmodule
module GP_IBUF(input IN, output OUT);
assign OUT = IN;
endmodule
module GP_IOBUF(input IN, input OE, output OUT, inout IO);
assign OUT = IO;
assign IO = OE ? IN : 1'bz;
endmodule
module GP_INV(input IN, output OUT);
assign OUT = ~IN;
endmodule
@ -153,6 +170,14 @@ module GP_LFOSC(input PWRDN, output reg CLKOUT);
endmodule
module GP_OBUF(input IN, output OUT);
assign OUT = IN;
endmodule
module GP_OBUFT(input IN, input OE, output OUT);
assign OUT = OE ? IN : 1'bz;
endmodule
module GP_PGA(input wire VIN_P, input wire VIN_N, input wire VIN_SEL, output reg VOUT);
parameter GAIN = 1;

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@ -176,6 +176,8 @@ struct SynthGreenPAK4Pass : public ScriptPass
if (check_label("map_cells"))
{
run("shregmap -tech greenpak4");
run("iopadmap -bits -inpad GP_IBUF OUT:IN -outpad GP_OBUF IN:OUT -inoutpad GP_IBUF OUT:IN");
run("extract -map +/greenpak4/cells_extract.v -verbose");
run("dfflibmap -liberty +/greenpak4/gp_dff.lib");
run("techmap -map +/greenpak4/cells_map.v");
run("dffinit -ff GP_DFF Q INIT");