stv0g/yosys
1
0
Fork 0
Code Issues Pull requests Releases Wiki Activity

Added $meminit cell type

Browse source
This commit is contained in:
Clifford Wolf 2015-02-14 10:23:03 +01:00
parent ef151b0b30
commit 910556560f
4 changed files with 33 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
kernel/celltypes.h
View file

@ -135,6 +135,7 @@ struct CellTypes
setup_type("$memrd", {CLK, ADDR}, {DATA});
setup_type("$memwr", {CLK, EN, ADDR, DATA}, pool<RTLIL::IdString>());
setup_type("$meminit", {ADDR, DATA}, pool<RTLIL::IdString>());
setup_type("$mem", {RD_CLK, RD_ADDR, WR_CLK, WR_EN, WR_ADDR, WR_DATA}, {RD_DATA});
setup_type("$fsm", {CLK, ARST, CTRL_IN}, {CTRL_OUT});

9
kernel/rtlil.cc
View file

@ -904,6 +904,15 @@ namespace {
return;
}
if (cell->type == "$meminit") {
param("\\MEMID");
param("\\PRIORITY");
port("\\ADDR", param("\\ABITS"));
port("\\DATA", param("\\WIDTH"));
check_expected();
return;
}
if (cell->type == "$mem") {
param("\\MEMID");
param("\\SIZE");

2
passes/opt/opt_clean.cc
View file

@ -47,7 +47,7 @@ void rmunused_module_cells(Module *module, bool verbose)
if (bit.wire != nullptr)
wire2driver[bit].insert(cell);
}
if (cell->type == "$memwr" || cell->type == "$assert" || cell->has_keep_attr())
if (cell->type.in("$memwr", "$meminit", "$assert") || cell->has_keep_attr())
queue.insert(cell);
else
unused.insert(cell);

22
techlibs/common/simlib.v
View file

@ -1514,6 +1514,28 @@ endmodule
// --------------------------------------------------------
module \$meminit (ADDR, DATA);
parameter MEMID = "";
parameter ABITS = 8;
parameter WIDTH = 8;
parameter PRIORITY = 0;
input [ABITS-1:0] ADDR;
input [WIDTH-1:0] DATA;
initial begin
if (MEMID != "") begin
$display("ERROR: Found non-simulatable instance of $meminit!");
$finish;
end
end
endmodule
// --------------------------------------------------------
module \$mem (RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);
parameter MEMID = "";