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Various bug fixes (related to $macc model testing)

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This commit is contained in:
Clifford Wolf 2014-09-06 20:30:46 +02:00
parent 98e6463ca7
commit 9329a76818
4 changed files with 5 additions and 4 deletions
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3
backends/verilog/verilog_backend.cc
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@ -973,7 +973,8 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
for (int i = 0; i < wire->width; i++)
if (reg_bits.count(std::pair<RTLIL::Wire*,int>(wire, i)) == 0)
goto this_wire_aint_reg;
reg_wires.insert(wire->name);
if (wire->width)
reg_wires.insert(wire->name);
this_wire_aint_reg:;
}
}

2
passes/tests/test_cell.cc
View file

@ -262,7 +262,7 @@ static void run_eval_test(RTLIL::Design *design, bool verbose, std::string uut_n
gold_ce.set(gold_wire, in_value);
gate_ce.set(gate_wire, in_value);
if (vlog_file.is_open()) {
if (vlog_file.is_open() && SIZE(in_value) > 0) {
vlog_file << stringf(" %s = 'b%s;\n", log_id(gold_wire), in_value.as_string().c_str());
if (!vlog_pattern_info.empty())
vlog_pattern_info += " ";

2
techlibs/common/simlib.v
View file

@ -768,7 +768,7 @@ module \$macc (A, B, Y);
localparam integer num_bits = CONFIG[3:0];
localparam integer num_ports = (CONFIG_WIDTH-4) / (2 + 2*num_bits);
localparam integer num_abits = $clog2(A_WIDTH);
localparam integer num_abits = $clog2(A_WIDTH) > 0 ? $clog2(A_WIDTH) : 1;
function [2*num_ports*num_abits-1:0] get_port_offsets;
input [CONFIG_WIDTH-1:0] cfg;

2
techlibs/common/techmap.v
View file

@ -594,7 +594,7 @@ module \$macc (A, B, Y);
localparam integer num_bits = CONFIG[3:0];
localparam integer num_ports = (CONFIG_WIDTH-4) / (2 + 2*num_bits);
localparam integer num_abits = $clog2(A_WIDTH);
localparam integer num_abits = $clog2(A_WIDTH) > 0 ? $clog2(A_WIDTH) : 1;
function [2*num_ports*num_abits-1:0] get_port_offsets;
input [CONFIG_WIDTH-1:0] cfg;