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Updated tech lib for greenpak4 counter with some clarifications

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This commit is contained in:
Andrew Zonenberg 2016-03-30 20:30:25 -07:00
parent dd7204c0bd
commit 94a6923e7d
1 changed files with 3 additions and 3 deletions
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6
techlibs/greenpak4/cells_sim.v
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@ -99,8 +99,8 @@ module GP_COUNT8(input CLK, input wire RST, output reg OUT);
OUT <= (count == 8'h0);
end
//datasheet is unclear but experimental testing confirms that POR value is COUNT_TO.
//Reset value is clearly 0 except in count/FSM cells where it's configurable.
//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
//Runtime reset value is clearly 0 except in count/FSM cells where it's configurable but we leave at 0 for now.
//Datasheet seems to indicate that reset is asynchronous, but for now we model as sync due to Yosys issues...
always @(posedge CLK) begin
@ -114,7 +114,7 @@ module GP_COUNT8(input CLK, input wire RST, output reg OUT);
count <= 0;
if((RESET_MODE == "FALLING") && !RST)
count <= 0;
if((RESET_MODE == "BITH") && RST)
if((RESET_MODE == "BOTH") && RST)
count <= 0;
*/
end