Fixed mem assignment in left-hand-side concatenation
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2 changed files with 57 additions and 0 deletions
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@ -1418,6 +1418,50 @@ skip_dynamic_range_lvalue_expansion:;
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goto apply_newNode;
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}
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// assignment with nontrivial member in left-hand concat expression -> split assignment
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if ((type == AST_ASSIGN_EQ || type == AST_ASSIGN_LE) && children[0]->type == AST_CONCAT && width_hint > 0)
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{
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bool found_nontrivial_member = false;
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for (auto child : children[0]->children) {
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if (child->type == AST_IDENTIFIER && child->id2ast != NULL && child->id2ast->type == AST_MEMORY)
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found_nontrivial_member = true;
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}
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if (found_nontrivial_member)
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{
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newNode = new AstNode(AST_BLOCK);
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AstNode *wire_tmp = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(width_hint-1, true), mkconst_int(0, true)));
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wire_tmp->str = stringf("$splitcmplxassign$%s:%d$%d", filename.c_str(), linenum, autoidx++);
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current_ast_mod->children.push_back(wire_tmp);
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current_scope[wire_tmp->str] = wire_tmp;
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wire_tmp->attributes["\\nosync"] = AstNode::mkconst_int(1, false);
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while (wire_tmp->simplify(true, false, false, 1, -1, false, false)) { }
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AstNode *wire_tmp_id = new AstNode(AST_IDENTIFIER);
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wire_tmp_id->str = wire_tmp->str;
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newNode->children.push_back(new AstNode(AST_ASSIGN_EQ, wire_tmp_id, children[1]->clone()));
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int cursor = 0;
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for (auto child : children[0]->children)
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{
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int child_width_hint = -1;
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bool child_sign_hint = true;
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child->detectSignWidth(child_width_hint, child_sign_hint);
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AstNode *rhs = wire_tmp_id->clone();
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rhs->children.push_back(new AstNode(AST_RANGE, AstNode::mkconst_int(cursor+child_width_hint-1, true), AstNode::mkconst_int(cursor, true)));
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newNode->children.push_back(new AstNode(type, child->clone(), rhs));
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cursor += child_width_hint;
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}
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goto apply_newNode;
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}
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}
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// assignment with memory in left-hand side expression -> replace with memory write port
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if (stage > 1 && (type == AST_ASSIGN_EQ || type == AST_ASSIGN_LE) && children[0]->type == AST_IDENTIFIER &&
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children[0]->id2ast && children[0]->id2ast->type == AST_MEMORY && children[0]->id2ast->children.size() >= 2 &&
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@ -264,3 +264,16 @@ module memtest11(clk, wen, waddr, raddr, wdata, rdata);
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end
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endmodule
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// ----------------------------------------------------------
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module memtest12 (
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input clk,
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input [1:0] adr,
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input [1:0] din,
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output reg [1:0] q
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);
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reg [1:0] ram [3:0];
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always@(posedge clk)
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{ram[adr], q} <= {din, ram[adr]};
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endmodule
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