From 8619d33114edc58d89247ac3471d4115e1689a82 Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Mon, 11 Jul 2016 22:42:25 -0700 Subject: [PATCH 1/3] Removed splitnets in prep for new gp4par parser --- techlibs/greenpak4/synth_greenpak4.cc | 1 - 1 file changed, 1 deletion(-) diff --git a/techlibs/greenpak4/synth_greenpak4.cc b/techlibs/greenpak4/synth_greenpak4.cc index 50820a60..c8f81a18 100644 --- a/techlibs/greenpak4/synth_greenpak4.cc +++ b/techlibs/greenpak4/synth_greenpak4.cc @@ -195,7 +195,6 @@ struct SynthGreenPAK4Pass : public ScriptPass if (check_label("json")) { - run("splitnets;;", "(temporary workaround for gp4par parser limitation)"); if (!json_file.empty() || help_mode) run(stringf("write_json %s", help_mode ? "" : json_file.c_str())); } From baae472b83b3dac1293bb95ff0a87d9180a67479 Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Mon, 11 Jul 2016 22:45:42 -0700 Subject: [PATCH 2/3] Removed VOUT port of GP_BANDGAP --- techlibs/greenpak4/cells_sim.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 67f00f3a..bf178a08 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -36,7 +36,7 @@ module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT endmodule -module GP_BANDGAP(output reg OK, output reg VOUT); +module GP_BANDGAP(output reg OK); parameter AUTO_PWRDN = 1; parameter CHOPPER_EN = 1; parameter OUT_DELAY = 100; From 52a738a54435d9e54ac7cb523551ae866cc76770 Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Mon, 11 Jul 2016 22:45:55 -0700 Subject: [PATCH 3/3] Added GP_DAC cell --- techlibs/greenpak4/cells_sim.v | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index bf178a08..ca8556a8 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -120,6 +120,14 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT, endmodule +module GP_DAC(input[7:0] DIN, input wire VREF, output reg VOUT); + + initial VOUT = 0; + + //analog hard IP is not supported for simulation + +endmodule + module GP_DELAY(input IN, output reg OUT); parameter DELAY_STEPS = 1;