diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index 04bce877..7555a7ac 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -17,6 +17,8 @@ module GP_ABUF(input wire IN, output wire OUT);
 	
 	assign OUT = IN;
 	
+	//cannot simulate mixed signal IP
+	
 endmodule
 
 module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT);