diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index 708ac762..0fd7c6e0 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -708,6 +708,8 @@ wire_name_and_opt_assign:
 
 wire_name:
 	TOK_ID range_or_multirange {
+		if (astbuf1 == nullptr)
+			frontend_verilog_yyerror("Syntax error.");
 		AstNode *node = astbuf1->clone();
 		node->str = *$1;
 		append_attr_clone(node, albuf);