From af15b92c861f11d1f4b5016fed0cb8cb45af9175 Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Sat, 26 Mar 2016 13:42:41 -0700 Subject: [PATCH 1/4] Renamed GP4_V* cells to GP_V* for consistency --- techlibs/greenpak4/cells_sim.v | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 4602c6cc..54e5a423 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -55,10 +55,11 @@ module GP_4LUT(input IN0, IN1, IN2, IN3, output OUT); assign OUT = INIT[{IN3, IN2, IN1, IN0}]; endmodule -module GP4_VDD(output OUT); +module GP_VDD(output OUT); assign OUT = 1; endmodule -module GP4_VSS(output OUT); +module GP_VSS(output OUT); assign OUT = 0; endmodule + From 44fd3cd149786bc3aaf180af8ec83f790d9cebbe Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Sat, 26 Mar 2016 13:42:53 -0700 Subject: [PATCH 2/4] Added GP_LFOSC cell --- techlibs/greenpak4/cells_sim.v | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 54e5a423..249ea286 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -63,3 +63,20 @@ module GP_VSS(output OUT); assign OUT = 0; endmodule +module GP_LFOSC(input PWRDN, output reg CLKOUT); + parameter PWRDN_EN = 0; + parameter AUTO_ON = 0; + + initial CLKOUT = 0; + + always begin + if(PWRDN) + clkout = 0; + else begin + //half period of 1730 Hz + #289017; + clkout = ~clkout; + end + end + +endmodule From 31a7567affb7425af1aa27d6dcda4666859ce62f Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Sat, 26 Mar 2016 14:13:52 -0700 Subject: [PATCH 3/4] Changed GP_LFOSC parameter configuration --- techlibs/greenpak4/cells_sim.v | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 249ea286..a4094f06 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -64,8 +64,10 @@ module GP_VSS(output OUT); endmodule module GP_LFOSC(input PWRDN, output reg CLKOUT); + parameter PWRDN_EN = 0; - parameter AUTO_ON = 0; + parameter AUTO_PWRDN = 0; + parameter OUT_DIV = 1; initial CLKOUT = 0; From 3197b6c3721b4985b5a5e4223ce7092e27f750c7 Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Sat, 26 Mar 2016 23:29:02 -0700 Subject: [PATCH 4/4] Added GP_COUNT8/GP_COUNT14 cells --- techlibs/greenpak4/cells_sim.v | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index a4094f06..6b5100f7 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -82,3 +82,25 @@ module GP_LFOSC(input PWRDN, output reg CLKOUT); end endmodule + +module GP_COUNT8(input CLK, input wire RST, output reg OUT); + + parameter RESET_MODE = "RISING"; + + parameter COUNT_TO = 8'h1; + parameter CLKIN_DIVIDE = 1; + + //more complex hard IP blocks are not supported for simulation yet + +endmodule + +module GP_COUNT14(input CLK, input wire RST, output reg OUT); + + parameter RESET_MODE = "RISING"; + + parameter COUNT_TO = 14'h1; + parameter CLKIN_DIVIDE = 1; + + //more complex hard IP blocks are not supported for simulation yet + +endmodule