stv0g/yosys
1
0
Fork 0
Code Issues Pull requests Releases Wiki Activity

Fixed keep attribute on wires in opt_clean

Browse source
This commit is contained in:
Clifford Wolf 2013-11-08 05:20:15 +01:00
parent 4abc8e695a
commit b04051a0e2
1 changed files with 1 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
passes/opt/opt_clean.cc
View file

@ -54,7 +54,7 @@ static void rmunused_module_cells(RTLIL::Module *module, bool verbose)
for (auto &it : module->wires) {
RTLIL::Wire *wire = it.second;
if (wire->port_output) {
if (wire->port_output || wire->get_bool_attribute("\\keep")) {
std::set<RTLIL::Cell*> cell_list;
RTLIL::SigSpec sig = RTLIL::SigSpec(wire);
assign_map.apply(sig);