Fixed bug in memory_share for memory ports with different ABITS
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1 changed files with 6 additions and 0 deletions
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@ -619,6 +619,12 @@ struct MemoryShareWorker
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RTLIL::SigBit this_en_active = module->ReduceOr(NEW_ID, this_en);
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if (GetSize(last_addr) < GetSize(this_addr))
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last_addr.extend_u0(GetSize(this_addr));
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else
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this_addr.extend_u0(GetSize(last_addr));
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wr_ports[i]->setParam("\\ABITS", GetSize(this_addr));
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wr_ports[i]->setPort("\\ADDR", module->Mux(NEW_ID, last_addr, this_addr, this_en_active));
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wr_ports[i]->setPort("\\DATA", module->Mux(NEW_ID, last_data, this_data, this_en_active));
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