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Some test related fixes

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(incl. removal of three bad test cases)
This commit is contained in:
Clifford Wolf 2015-02-12 17:45:44 +01:00
parent 554a8df5e2
commit d58c3eca3a
6 changed files with 6 additions and 156 deletions
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2
passes/tests/test_autotb.cc
View file

@ -195,7 +195,7 @@ static void autotest(std::ostream &f, RTLIL::Design *design, int num_iter)
f << stringf(" } = {");
for (auto it = signal_clk.begin(); it != signal_clk.end(); it++)
f << stringf("%s %s", it == signal_clk.begin() ? "" : ",", it->first.c_str());
f << stringf(" } ^ (%d'b1 << (xorshift128_w %% %d));\n", total_clock_bits, total_clock_bits);
f << stringf(" } ^ (%d'b1 << (xorshift128_w %% %d));\n", total_clock_bits, total_clock_bits + 1);
}
f << stringf("end\n");
f << stringf("endtask\n\n");

8
techlibs/common/simlib.v
View file

@ -1328,7 +1328,7 @@ output reg [WIDTH-1:0] Q;
always @* begin
if (EN == EN_POLARITY)
Q <= D;
Q = D;
end
endmodule
@ -1356,11 +1356,11 @@ generate
for (i = 0; i < WIDTH; i = i+1) begin:bit
always @*
if (pos_clr[i])
Q[i] <= 0;
Q[i] = 0;
else if (pos_set[i])
Q[i] <= 1;
Q[i] = 1;
else if (pos_en)
Q[i] <= D[i];
Q[i] = D[i];
end
endgenerate

30
tests/asicworld/code_hdl_models_dlatch_reset.v
View file

@ -1,30 +0,0 @@
//-----------------------------------------------------
// Design Name : dlatch_reset
// File Name : dlatch_reset.v
// Function : DLATCH async reset
// Coder : Deepak Kumar Tala
//-----------------------------------------------------
module dlatch_reset (
data , // Data Input
en , // LatchInput
reset , // Reset input
q // Q output
);
//-----------Input Ports---------------
input data, en, reset ;
//-----------Output Ports---------------
output q;
//------------Internal Variables--------
reg q;
//-------------Code Starts Here---------
always @ ( en or reset or data)
if (~reset) begin
q <= 1'b0;
end else if (en) begin
q <= data;
end
endmodule //End Of Module dlatch_reset

58
tests/asicworld/code_hdl_models_ram_sp_ar_sw.v
View file

@ -1,58 +0,0 @@
//-----------------------------------------------------
// Design Name : ram_sp_ar_sw
// File Name : ram_sp_ar_sw.v
// Function : Asynchronous read write RAM
// Coder : Deepak Kumar Tala
//-----------------------------------------------------
module ram_sp_ar_sw (
clk , // Clock Input
address , // Address Input
data , // Data bi-directional
cs , // Chip Select
we , // Write Enable/Read Enable
oe // Output Enable
);
parameter DATA_WIDTH = 8 ;
parameter ADDR_WIDTH = 8 ;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
//--------------Input Ports-----------------------
input clk ;
input [ADDR_WIDTH-1:0] address ;
input cs ;
input we ;
input oe ;
//--------------Inout Ports-----------------------
inout [DATA_WIDTH-1:0] data ;
//--------------Internal variables----------------
reg [DATA_WIDTH-1:0] data_out ;
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
//--------------Code Starts Here------------------
// Tri-State Buffer control
// output : When we = 0, oe = 1, cs = 1
assign data = (cs && oe && !we) ? data_out : 8'bz;
// Memory Write Block
// Write Operation : When we = 1, cs = 1
always @ (posedge clk)
begin : MEM_WRITE
if ( cs && we ) begin
mem[address] = data;
end
end
// Memory Read Block
// Read Operation : When we = 0, oe = 1, cs = 1
always @ (address or cs or we or oe)
begin : MEM_READ
if (cs && !we && oe) begin
data_out = mem[address];
end
end
endmodule // End of Module ram_sp_ar_sw

62
tests/asicworld/code_hdl_models_ram_sp_sr_sw.v
View file

@ -1,62 +0,0 @@
//-----------------------------------------------------
// Design Name : ram_sp_sr_sw
// File Name : ram_sp_sr_sw.v
// Function : Synchronous read write RAM
// Coder : Deepak Kumar Tala
//-----------------------------------------------------
module ram_sp_sr_sw (
clk , // Clock Input
address , // Address Input
data , // Data bi-directional
cs , // Chip Select
we , // Write Enable/Read Enable
oe // Output Enable
);
parameter DATA_WIDTH = 8 ;
parameter ADDR_WIDTH = 8 ;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
//--------------Input Ports-----------------------
input clk ;
input [ADDR_WIDTH-1:0] address ;
input cs ;
input we ;
input oe ;
//--------------Inout Ports-----------------------
inout [DATA_WIDTH-1:0] data ;
//--------------Internal variables----------------
reg [DATA_WIDTH-1:0] data_out ;
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
reg oe_r;
//--------------Code Starts Here------------------
// Tri-State Buffer control
// output : When we = 0, oe = 1, cs = 1
assign data = (cs && oe && !we) ? data_out : 8'bz;
// Memory Write Block
// Write Operation : When we = 1, cs = 1
always @ (posedge clk)
begin : MEM_WRITE
if ( cs && we ) begin
mem[address] = data;
end
end
// Memory Read Block
// Read Operation : When we = 0, oe = 1, cs = 1
always @ (posedge clk)
begin : MEM_READ
if (cs && !we && oe) begin
data_out = mem[address];
oe_r = 1;
end else begin
oe_r = 0;
end
end
endmodule // End of Module ram_sp_sr_sw

2
tests/tools/autotest.sh
View file

@ -145,7 +145,7 @@ do
elif [ "$frontend" = "verific_gates" ]; then
test_passes -p "verific -vlog2k $fn; verific -import -gates -all; opt; memory;;"
else
test_passes -f "$frontend" -p "hierarchy; proc; opt; memory; opt; fsm; opt -fine" $fn
test_passes -f "$frontend" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" $fn
test_passes -f "$frontend" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" $fn
fi
touch ../${bn}.log