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After reading the SV spec, using non-standard predict() instead of expect()

This commit is contained in:
Clifford Wolf 2016-07-21 13:34:33 +02:00
parent 721f1f5ecf
commit d7763634b6
16 changed files with 28 additions and 32 deletions
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4
README
View File

@ -384,8 +384,8 @@ from SystemVerilog:
form. In module context: "assert property (<expression>);" and within an
always block: "assert(<expression>);". It is transformed to a $assert cell.
- The "assume" and "expect" statements from SystemVerilog are also
supported. The same limitations as with the "assert" statement apply.
- The "assume" statements from SystemVerilog are also supported. The same
limitations as with the "assert" statement apply.
- The keywords "always_comb", "always_ff" and "always_latch", "logic" and
"bit" are supported.

2
examples/smtbmc/demo1.v
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@ -8,7 +8,7 @@ module demo1(input clk, input addtwo, output iseven);
cnt = (iseven ? cnt == 10 : cnt == 11) ? 0 : next_cnt;
assert property (cnt != 15);
// initial expect ((iseven && addtwo) || cnt == 9);
// initial predict ((iseven && addtwo) || cnt == 9);
endmodule
module inc(input addtwo, output iseven, input [3:0] a, output [3:0] y);

2
frontends/ast/ast.cc
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@ -82,7 +82,7 @@ std::string AST::type2str(AstNodeType type)
X(AST_PREFIX)
X(AST_ASSERT)
X(AST_ASSUME)
X(AST_EXPECT)
X(AST_PREDICT)
X(AST_FCALL)
X(AST_TO_BITS)
X(AST_TO_SIGNED)

2
frontends/ast/ast.h
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@ -65,7 +65,7 @@ namespace AST
AST_PREFIX,
AST_ASSERT,
AST_ASSUME,
AST_EXPECT,
AST_PREDICT,
AST_FCALL,
AST_TO_BITS,

4
frontends/ast/genrtlil.cc
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@ -1296,11 +1296,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
// generate $assert cells
case AST_ASSERT:
case AST_ASSUME:
case AST_EXPECT:
case AST_PREDICT:
{
const char *celltype = "$assert";
if (type == AST_ASSUME) celltype = "$assume";
if (type == AST_EXPECT) celltype = "$expect";
if (type == AST_PREDICT) celltype = "$predict";
log_assert(children.size() == 2);

4
frontends/ast/simplify.cc
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@ -1348,7 +1348,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
}
skip_dynamic_range_lvalue_expansion:;
if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME || type == AST_EXPECT) && current_block != NULL)
if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME || type == AST_PREDICT) && current_block != NULL)
{
std::stringstream sstr;
sstr << "$formal$" << filename << ":" << linenum << "$" << (autoidx++);
@ -1405,7 +1405,7 @@ skip_dynamic_range_lvalue_expansion:;
goto apply_newNode;
}
if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME || type == AST_EXPECT) && children.size() == 1)
if (stage > 1 && (type == AST_ASSERT || type == AST_ASSUME || type == AST_PREDICT) && children.size() == 1)
{
children.push_back(mkconst_int(1, false, 1));
did_something = true;

6
frontends/verilog/verilog_lexer.l
View File

@ -63,6 +63,10 @@ YOSYS_NAMESPACE_END
frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext); \
return TOK_ID;
#define NON_KEYWORD() \
frontend_verilog_yylval.string = new std::string(std::string("\\") + yytext); \
return TOK_ID;
#define YY_INPUT(buf,result,max_size) \
result = readsome(*VERILOG_FRONTEND::lexin, buf, max_size)
@ -173,7 +177,7 @@ YOSYS_NAMESPACE_END
"assert" { if (formal_mode) return TOK_ASSERT; SV_KEYWORD(TOK_ASSERT); }
"assume" { if (formal_mode) return TOK_ASSUME; SV_KEYWORD(TOK_ASSUME); }
"expect" { if (formal_mode) return TOK_EXPECT; SV_KEYWORD(TOK_EXPECT); }
"predict" { if (formal_mode) return TOK_PREDICT; NON_KEYWORD(); }
"property" { if (formal_mode) return TOK_PROPERTY; SV_KEYWORD(TOK_PROPERTY); }
"logic" { SV_KEYWORD(TOK_REG); }
"bit" { SV_KEYWORD(TOK_REG); }

10
frontends/verilog/verilog_parser.y
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@ -113,7 +113,7 @@ static void free_attr(std::map<std::string, AstNode*> *al)
%token TOK_SYNOPSYS_FULL_CASE TOK_SYNOPSYS_PARALLEL_CASE
%token TOK_SUPPLY0 TOK_SUPPLY1 TOK_TO_SIGNED TOK_TO_UNSIGNED
%token TOK_POS_INDEXED TOK_NEG_INDEXED TOK_ASSERT TOK_ASSUME
%token TOK_EXPECT TOK_PROPERTY
%token TOK_PREDICT TOK_PROPERTY
%type <ast> range range_or_multirange non_opt_range non_opt_multirange range_or_signed_int
%type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list
@ -967,8 +967,8 @@ assert:
TOK_ASSUME '(' expr ')' ';' {
ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $3));
} |
TOK_EXPECT '(' expr ')' ';' {
ast_stack.back()->children.push_back(new AstNode(AST_EXPECT, $3));
TOK_PREDICT '(' expr ')' ';' {
ast_stack.back()->children.push_back(new AstNode(AST_PREDICT, $3));
};
assert_property:
@ -978,8 +978,8 @@ assert_property:
TOK_ASSUME TOK_PROPERTY '(' expr ')' ';' {
ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $4));
} |
TOK_EXPECT TOK_PROPERTY '(' expr ')' ';' {
ast_stack.back()->children.push_back(new AstNode(AST_EXPECT, $4));
TOK_PREDICT TOK_PROPERTY '(' expr ')' ';' {
ast_stack.back()->children.push_back(new AstNode(AST_PREDICT, $4));
};
simple_behavioral_stmt:

2
kernel/celltypes.h
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@ -116,7 +116,7 @@ struct CellTypes
setup_type("$assert", {A, EN}, pool<RTLIL::IdString>(), true);
setup_type("$assume", {A, EN}, pool<RTLIL::IdString>(), true);
setup_type("$expect", {A, EN}, pool<RTLIL::IdString>(), true);
setup_type("$predict", {A, EN}, pool<RTLIL::IdString>(), true);
setup_type("$equiv", {A, B}, {Y}, true);
}

4
kernel/rtlil.cc
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@ -1017,7 +1017,7 @@ namespace {
return;
}
if (cell->type.in("$assert", "$assume", "$expect")) {
if (cell->type.in("$assert", "$assume", "$predict")) {
port("\\A", 1);
port("\\EN", 1);
check_expected();
@ -1798,7 +1798,7 @@ RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a
RTLIL::Cell* RTLIL::Module::addExpect(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en)
{
RTLIL::Cell *cell = addCell(name, "$expect");
RTLIL::Cell *cell = addCell(name, "$predict");
cell->setPort("\\A", sig_a);
cell->setPort("\\EN", sig_en);
return cell;

2
kernel/satgen.h
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@ -1347,7 +1347,7 @@ struct SatGen
return true;
}
if (cell->type == "$expect")
if (cell->type == "$predict")
{
std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep));
expects_a[pf].append((*sigmap)(cell->getPort("\\A")));

2
manual/CHAPTER_CellLib.tex
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@ -421,7 +421,7 @@ pass. The combinatorial logic cells can be mapped to physical cells from a Liber
using the {\tt abc} pass.
\begin{fixme}
Add information about {\tt \$assert}, {\tt \$assume}, {\tt \$expect}, and {\tt \$equiv} cells.
Add information about {\tt \$assert}, {\tt \$assume}, {\tt \$predict}, and {\tt \$equiv} cells.
\end{fixme}
\begin{fixme}

2
passes/hierarchy/hierarchy.cc
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@ -313,7 +313,7 @@ bool set_keep_assert(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod)
if (cache.count(mod) == 0)
for (auto c : mod->cells()) {
RTLIL::Module *m = mod->design->module(c->type);
if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in("$assert", "$assume", "$expect"))
if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in("$assert", "$assume", "$predict"))
return cache[mod] = true;
}
return cache[mod];

2
passes/opt/opt_clean.cc
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@ -64,7 +64,7 @@ struct keep_cache_t
bool query(Cell *cell)
{
if (cell->type.in("$memwr", "$meminit", "$assert", "$assume", "$expect"))
if (cell->type.in("$memwr", "$meminit", "$assert", "$assume", "$predict"))
return true;
if (cell->has_keep_attr())

2
passes/tests/test_cell.cc
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@ -731,7 +731,7 @@ struct TestCellPass : public Pass {
// cell_types["$concat"] = "A";
// cell_types["$assert"] = "A";
// cell_types["$assume"] = "A";
// cell_types["$expect"] = "A";
// cell_types["$predict"] = "A";
cell_types["$lut"] = "*";
cell_types["$sop"] = "*";

10
techlibs/common/simlib.v
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@ -1305,18 +1305,10 @@ endmodule
// --------------------------------------------------------
module \$expect (A, EN);
module \$predict (A, EN);
input A, EN;
`ifndef SIMLIB_NOCHECKS
always @* begin
if (A === 1'b1 && EN === 1'b1) begin
$display("Expectation %m passed.");
end
end
`endif
endmodule
// --------------------------------------------------------