SystemVerilog also has assume(), added implicit -D FORMAL
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34f34be17c
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3 changed files with 5 additions and 4 deletions
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@ -39,6 +39,7 @@
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#include <string.h>
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YOSYS_NAMESPACE_BEGIN
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using namespace VERILOG_FRONTEND;
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static std::list<std::string> output_code;
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static std::list<std::string> input_buffer;
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@ -222,7 +223,7 @@ std::string frontend_verilog_preproc(std::istream &f, std::string filename, cons
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input_file(f, filename);
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defines_map["YOSYS"] = "1";
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defines_map["SYNTHESIS"] = "1";
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defines_map[formal_mode ? "FORMAL" : "SYNTHESIS"] = "1";
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while (!input_buffer.empty())
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{
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@ -63,8 +63,8 @@ struct VerilogFrontend : public Frontend {
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log(" of SystemVerilog is supported)\n");
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log("\n");
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log(" -formal\n");
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log(" enable support for assert() and assume() statements\n");
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log(" (assert support is also enabled with -sv)\n");
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log(" enable support for assert() and assume() from SystemVerilog\n");
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log(" replace the implicit -D SYNTHESIS with -D FORMAL\n");
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log("\n");
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log(" -dump_ast1\n");
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log(" dump abstract syntax tree (before simplification)\n");
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@ -170,7 +170,7 @@ YOSYS_NAMESPACE_END
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"always_latch" { SV_KEYWORD(TOK_ALWAYS); }
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"assert" { if (formal_mode) return TOK_ASSERT; SV_KEYWORD(TOK_ASSERT); }
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"assume" { if (formal_mode) return TOK_ASSUME; return TOK_ID; }
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"assume" { if (formal_mode) return TOK_ASSUME; SV_KEYWORD(TOK_ASSUME); }
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"property" { if (formal_mode) return TOK_PROPERTY; SV_KEYWORD(TOK_PROPERTY); }
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"logic" { SV_KEYWORD(TOK_REG); }
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"bit" { SV_KEYWORD(TOK_REG); }
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