From a0c19aae55d878576c7481a6a4a5d10ba98c5224 Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Sat, 7 May 2016 21:13:47 -0700 Subject: [PATCH 1/5] Added simulation timescale declaration --- techlibs/greenpak4/cells_sim.v | 2 ++ 1 file changed, 2 insertions(+) diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 6cf29fe6..da370463 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -1,3 +1,5 @@ +`timescale 1ns/1ps; + module GP_2LUT(input IN0, IN1, output OUT); parameter [3:0] INIT = 0; assign OUT = INIT[{IN1, IN0}]; From 85ee88b0ee13eb49bb255d7e66a62fce823c028a Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Sat, 7 May 2016 21:14:00 -0700 Subject: [PATCH 2/5] Fixed typo in parameter name --- techlibs/greenpak4/cells_sim.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index da370463..c4e5a9de 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -69,7 +69,7 @@ module GP_COUNT8(input CLK, input wire RST, output reg OUT); count <= count - 1'd1; if(count == 0) - count <= COUNT_MAX; + count <= COUNT_TO; /* if((RESET_MODE == "RISING") && RST) From b5171541cd9da6a4e2b5aaaaf3bca76e059c7e3f Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Sat, 7 May 2016 21:14:18 -0700 Subject: [PATCH 3/5] Fixed extra semicolon --- techlibs/greenpak4/cells_sim.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index c4e5a9de..5a59a06b 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -1,4 +1,4 @@ -`timescale 1ns/1ps; +`timescale 1ns/1ps module GP_2LUT(input IN0, IN1, output OUT); parameter [3:0] INIT = 0; From 41bbad4e4c25bc1b0227348ec0329187c8688c4b Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Sat, 7 May 2016 21:14:42 -0700 Subject: [PATCH 4/5] Fixed typo in port name --- techlibs/greenpak4/cells_sim.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 5a59a06b..b9cfbe66 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -286,7 +286,7 @@ module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB); reg[15:0] shreg = 0; - always @(posedge clk, negedge nRST) begin + always @(posedge CLK, negedge nRST) begin if(!nRST) shreg = 0; From 47eace0b9f2b9ddd7ae76e06e2ade85ceea88e17 Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Sat, 7 May 2016 21:29:26 -0700 Subject: [PATCH 5/5] Added GP_DELAY cell --- techlibs/greenpak4/cells_sim.v | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index b9cfbe66..be8e66c6 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -94,6 +94,35 @@ module GP_COUNT14(input CLK, input wire RST, output reg OUT); endmodule +module GP_DELAY(input IN, output reg OUT); + + parameter DELAY_STEPS = 1; + + //TODO: additional delay/glitch filter mode + + initial OUT = 0; + + generate + + //TODO: These delays are PTV dependent! For now, hard code 3v3 timing + //Change simulation-mode delay depending on global Vdd range (how to specify this?) + always @(*) begin + case(DELAY_STEPS) + 1: #166 OUT = IN; + 2: #318 OUT = IN; + 2: #471 OUT = IN; + 3: #622 OUT = IN; + default: begin + $display("ERROR: GP_DELAY must have DELAY_STEPS in range [1,4]"); + $finish; + end + endcase + end + + endgenerate + +endmodule + module GP_DFF(input D, CLK, output reg Q); parameter [0:0] INIT = 1'bx; initial Q = INIT;